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| regarding the change of names mentioned in the document, such as hitachi electric and hitachi xx, to renesas technology corp. the semiconductor operations of mitsubishi electric and hitachi were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although hitachi, hitachi, ltd., hitachi semiconductors, and other hitachi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. renesas technology home page: http://www.renesas.com renesas technology corp. customer support dept. april 1, 2003 to all our customers
cautions keep safety first in your circuit designs! 1. renesas technology corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corporation or a third party. 2. renesas technology corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by renesas technology corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact renesas technology corporation or an authorized renesas technology corporation product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corporation by various means, including the renesas technology corporation semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact renesas technology corporation or an authorized renesas technology corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corporation is n ecessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corporation for further details on these materials or the products contained therein. superh tm risc engine peripheral lsi hd64413a q2sd quick 2d graphics renderer with synchronous dram interface users manual ade-602-204a rev. 2.0 09/24/02 hitachi, ltd. rev. 2.0, 09/02, page ii of xviii cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachis or any third partys patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third partys rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachis sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachis sales office for any questions regarding this document or hitachi semiconductor products. rev. 2.0, 09/02, page iii of xviii general precautions on handling of product 1. treatment of nc pins note: do not connect anything to the nc pins. the nc (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. if something is connected to the nc pins, the operation of the lsi is not guaranteed. 2. treatment of unused input pins note: fix all unused input pins to high or low level. generally, the input pins of cmos products are high-impedance input pins. if unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a pass- through current flows internally, and a malfunction may occur. 3. processing before initialization note: when power is first supplied, the products state is undefined. the states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. during the period where the states are undefined, the register settings and the output state of each pin are also undefined. design your system so that it does not malfunction because of processing while it is in this undefined state. for those products which have a reset function, reset the lsi immediately after the power supply has been turned on. 4. prohibition of access to undefined or reserved addresses note: access to undefined or reserved addresses is prohibited. the undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. do not access these registers; the systems operation is not guaranteed if they are accessed. rev. 2.0, 09/02, page iv of xviii configuration of this manual this manual comprises the following items: 1. general precautions on handling of product 2. configuration of this manual 3. preface 4. contents 5. overview 6. description of pins ? pin configuration ? pin arrangement ? pin functions 7. description of ugm architecture 8. description of display list the configuration of the functional description of each command differs according to the command. however, the generic style includes the following items: i) function ii) command format iii) command description iv) example 9. descriptions of registers ? list of registers ? descriptions of registers 10. usage notes when designing an application system that includes this lsi, take notes into account. each section includes notes in relation to the descriptions given, and usage notes are given. 11. electrical characteristics 12. appendix rev. 2.0, 09/02, page v of xviii preface the q2sd (quick 2d graphics renderer with synchronous dram interface) is a 2d graphics renderer that supports sdram interface in the sh microcomputer graphics accelerator quick series (q series), based on the concepts of simplicity, realtime operation, and upgradability. the q2sd is a high-performance graphics rendering lsi for multimedia applications, which provides both drawing and display, video input functions integrated into a single chip. target users: this manual was written for users who will be using the q2sd series in the design of application systems. target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. objective: this manual was written to explain the hardware functions and electrical characteristics of the q2sd series to the target users. in this revised version, descriptions of the video input function, the list of related manuals, and points to have gotten questions from customers are reviewed. notes on reading this manual: read the manual according to the contents. this manual can be roughly categorized into parts on overview, descriptions of the ugm architecture, display list, and registers, and usage notes. these are arranged in that order. rules: number notation: binary is b xxxx, hexadecimal is h xxxx. signal notation: an overbar is added to a low-active signal: [[[[ related manuals: the latest versions of all related manuals are available from our web site. please ensure you have the latest versions of all documents you require. http://www.hitachisemiconductor.com/ q2sd series manuals: manual title ade no. q2sd series hardware manual this manual application notes: manual title ade no. hd64413a q2sd application notes/q & a ade-502-070 rev. 2.0, 09/02, page vi of xviii contents section 1 overview ....................................................................................... 1 1.1 features.................................................................................................................... ... 2 1.2 a list of specifications................................................................................................ 9 1.3 block diagram............................................................................................................. 10 1.4 processing states ......................................................................................................... 13 1.4.1 power on ........................................................................................................ 13 1.4.2 initial states (when specified power is supplied)............................................. 13 1.4.3 reset state (when low level is input to 5(6(7 pin) ...................................... 14 1.4.4 ugm initialization state .................................................................................. 14 1.4.5 normal operating state ................................................................................... 14 section 2 pins................................................................................................ 15 2.1 pin configuration......................................................................................................... 15 2.2 pin arrangement.......................................................................................................... 16 2.3 pin functions............................................................................................................... 17 2.4 system control pins..................................................................................................... 23 2.4.1 operating mode pins....................................................................................... 23 2.4.2 clock pins....................................................................................................... 23 2.4.3 reset pin......................................................................................................... 25 2.4.4 power supply pin ............................................................................................ 25 2.5 cpu interface pins....................................................................................................... 26 2.5.1 cpu writes..................................................................................................... 26 2.5.2 cpu reads...................................................................................................... 26 2.5.3 dma writes .................................................................................................... 27 2.5.4 interrupts......................................................................................................... 28 2.6 ugm interface pins ..................................................................................................... 28 2.7 display interface pins .................................................................................................. 28 2.7.1 display signal output ..................................................................................... 28 2.7.2 video encoder interface .................................................................................. 29 2.7.3 crt interface.................................................................................................. 29 2.7.4 d/a converter................................................................................................. 29 2.8 video interface pins..................................................................................................... 30 2.8.1 video input interface ....................................................................................... 30 section 3 ugm architecture ......................................................................... 33 3.1 features.................................................................................................................... ... 33 3.2 q2sd access............................................................................................................... 34 3.2.1 ugm access priority ...................................................................................... 34 3.2.2 ugm access by the cpu ................................................................................ 35 rev. 2.0, 09/02, page vii of xviii 3.2.3 ugm access by dmac ..................................................................................35 3.2.4 ugm access by q2sd ....................................................................................35 3.2.5 register access from the cpu .........................................................................36 3.2.6 register updating............................................................................................37 3.2.7 byte exchange function ..................................................................................39 3.2.8 2-dimensional image data exchange function ................................................40 3.2.9 input color data configurations ......................................................................44 3.2.10 configurations of data in ugm .......................................................................47 3.2.11 q2sd internal data format .............................................................................49 3.2.12 interrupt output function ................................................................................50 3.3 unified graphics memory (ugm) ................................................................................51 3.3.1 memory address .............................................................................................51 3.3.2 memory map...................................................................................................56 3.3.3 coordinate systems .........................................................................................59 3.3.4 double-buffering control ................................................................................68 3.3.5 refresh control ...............................................................................................74 3.4 display ..................................................................................................................... ...75 3.4.1 display functions............................................................................................75 3.4.2 screen display composition ............................................................................78 3.4.3 scanning systems............................................................................................81 3.4.4 synchronization systems .................................................................................90 3.4.5 color expansion of display screen..................................................................94 3.5 rendering ................................................................................................................... .96 3.5.1 commands ......................................................................................................96 3.5.2 image data reference......................................................................................98 3.5.3 rendering attributes........................................................................................101 3.5.4 command fetching..........................................................................................110 3.5.5 internal buffer.................................................................................................113 3.6 video capture..............................................................................................................1 14 3.6.1 configuring circuit for video capture .............................................................114 3.6.2 video capture mode........................................................................................116 3.6.3 reduction of video capture images.................................................................122 3.6.4 setting video capture position ........................................................................123 3.6.5 format of captured data..................................................................................125 3.6.6 ycbcr and rgb data .....................................................................................127 3.7 video display function................................................................................................128 3.7.1 video screen display ......................................................................................128 3.7.2 relationship between the display mode and video-capture mode ...................129 section 4 display list ....................................................................................137 4.1 four-vertex screen drawing ........................................................................................138 4.1.1 polygon4a .................................................................................................138 4.1.2 polygon4b .................................................................................................143 rev. 2.0, 09/02, page viii of xviii 4.1.3 polygon4c ................................................................................................. 147 4.2 line drawing............................................................................................................... 1 51 4.2.1 line............................................................................................................... 151 4.2.2 rline ............................................................................................................ 154 4.2.3 pline............................................................................................................. 156 4.2.4 rpline .......................................................................................................... 159 4.3 work screen drawing command ................................................................................. 162 4.3.1 ftrap............................................................................................................ 162 4.3.2 rftrap ......................................................................................................... 165 4.3.3 clrw ............................................................................................................ 168 4.4 work line drawing ..................................................................................................... 170 4.4.1 linew ........................................................................................................... 170 4.4.2 rlinew......................................................................................................... 173 4.5 register setting commands ......................................................................................... 175 4.5.1 move ............................................................................................................ 175 4.5.2 rmove .......................................................................................................... 177 4.5.3 lcofs............................................................................................................ 179 4.5.4 rlcofs ......................................................................................................... 181 4.5.5 sclip ............................................................................................................. 183 4.5.6 uclip ............................................................................................................ 185 4.5.7 wpr ............................................................................................................... 187 4.6 sequence control commands....................................................................................... 189 4.6.1 jump .............................................................................................................. 189 4.6.2 gosub ........................................................................................................... 191 4.6.3 ret ................................................................................................................ 194 4.6.4 nop3 .............................................................................................................. 195 4.6.5 vbkem.......................................................................................................... 196 4.6.6 trap.............................................................................................................. 197 section 5 registers ........................................................................................ 199 5.1 register map ............................................................................................................... 1 99 5.2 interface control registers........................................................................................... 202 5.2.1 system control register (sysr) ..................................................................... 203 5.2.2 status register (sr) ........................................................................................ 209 5.2.3 status register clear register (srcr) ............................................................. 213 5.2.4 interrupt enable register (ier)........................................................................ 214 5.2.5 memory mode register (memr).................................................................... 216 5.2.6 display mode register (dsmr) ...................................................................... 218 5.2.7 display mode 2 register (dsmr2) ................................................................ 222 5.2.8 rendering mode register (remr) .................................................................. 225 5.2.9 input data conversion mode register (iemr) ................................................. 227 5.2.10 video incorporation mode register (vimr) .................................................... 230 5.3 memory control registers ........................................................................................... 234 rev. 2.0, 09/02, page ix of xviii 5.3.1 display size registers (dsr) ..........................................................................234 5.3.2 display address registers (dsar) ..................................................................235 5.3.3 display list start address registers (dlsar).................................................236 5.3.4 multi-valued source area start address register (ssar) ...............................237 5.3.5 work area start address register (wsar) .....................................................238 5.3.6 background start coordinate registers (bgsr) ...............................................239 5.3.7 video area start address registers (vsar) ....................................................240 5.3.8 video window size registers (vsizer) .........................................................242 5.3.9 cursor area start address register (csar) .....................................................243 5.3.10 rendering start address register (rsar) .......................................................244 5.4 display control registers.............................................................................................244 5.4.1 display window registers (dswr) ................................................................245 5.4.2 horizontal sync pulse width register (hswr) ...............................................247 5.4.3 horizontal scan cycle register (hcr) ............................................................247 5.4.4 vertical start position register (vspr) ...........................................................247 5.4.5 vertical scan cycle register (vcr) ................................................................248 5.4.6 display off output registers (door) .............................................................249 5.4.7 color detection registers (cder)...................................................................250 5.4.8 equalizing pulse width register (eqwr) .......................................................250 5.4.9 separation width register (spwr)..................................................................251 5.4.10 video display start position registers (vpr) ..................................................252 5.4.11 cursor display start position registers (csr) .................................................253 5.4.12 color palette registers (cp000r to cp255r) ...................................................255 5.5 rendering control registers.........................................................................................257 5.5.1 command status registers (cstr)..................................................................257 5.5.2 current pointer registers (curr) ...................................................................258 5.5.3 local offset registers (lcor)........................................................................259 5.5.4 user clipping area registers (uclr) .............................................................259 5.5.5 system clipping area registers (sclr)..........................................................261 5.5.6 return address registers (rtnr) ...................................................................261 5.5.7 color offset register (color).......................................................................262 5.6 data transfer control registers ....................................................................................263 5.6.1 dma transfer start address registers (dmasr) ...........................................263 5.6.2 dma transfer word count registers (dmawr) ............................................264 5.6.3 image data transfer start address registers (isar)........................................265 5.6.4 image data size registers (idsr) ...................................................................266 5.6.5 image data entry register (ider)...................................................................267 section 6 usage notes....................................................................................269 6.1 power-on sequence .....................................................................................................269 6.2 use of 64-mbit sdram ( 16 type) ............................................................................270 6.3 cpu interface unit fifo .............................................................................................271 6.4 video fetching start timing ........................................................................................272 rev. 2.0, 09/02, page x of xviii 6.5 drawing using linear format source .......................................................................... 272 6.6 sdram mode register values for ugm set by q2sd ............................................... 273 section 7 electrical characteristics ................................................................ 275 7.1 absolute maximum ratings......................................................................................... 275 7.2 recommended operating conditions ........................................................................... 275 7.3 electrical characteristics test methods ........................................................................ 276 7.3.1 timing testing................................................................................................ 276 7.3.2 test load circuit (all output and input/output pins) ...................................... 277 7.4 electrical characteristics.............................................................................................. 278 7.4.1 dc characteristics........................................................................................... 278 7.4.2 ac characteristics........................................................................................... 280 7.5 timing charts.............................................................................................................. 2 88 7.5.1 clocks............................................................................................................. 288 7.5.2 reset timing................................................................................................... 288 7.5.3 cpu read cycle timing ................................................................................. 289 7.5.4 cpu write cycle timing................................................................................. 290 7.5.5 dma write cycle timing (dmac ? q2sd) ................................................. 291 7.5.6 interrupt output timing................................................................................... 295 7.5.7 ugm read cycle timing ................................................................................ 296 7.5.8 ugm write cycle timing ............................................................................... 297 7.5.9 ugm refresh cycle timing and mode register setting timing ...................... 298 7.5.10 master mode display timing .......................................................................... 300 7.5.11 tv sync mode display timing ....................................................................... 301 7.5.12 video interface timing.................................................................................... 303 appendix a initial register values................................................................ 305 appendix b commands and parameters ........................................................ 306 b.1 relationship between commands and rendering attributes.......................................... 306 b.2 command codes.......................................................................................................... 307 b.3 command parameter specifications ............................................................................. 308 appendix c drawing algorithms .................................................................. 316 appendix d package dimensions .................................................................. 319 appendix e display operating clock and screen synthesis .......................... 320 appendix f example of system configuration for superh............................ 325 f.1 determination of clock................................................................................................ 326 f.2 setting of software weight .......................................................................................... 327 f.3 special notes on connection ........................................................................................ 328 rev. 2.0, 09/02, page xi of xviii f.4 initialization procedures of address-mapped register ..................................................328 f.5 memory assignment ....................................................................................................329 f.5.1 memory mapping of hd64413a .....................................................................329 f.5.2 example of area placement in ugm ...............................................................330 f.5.3 address seriation in ugm ...............................................................................332 f.6 special notes on data transfer to ugm.......................................................................333 appendix g example of display control .......................................................334 g.1 determination of display size......................................................................................334 g.2 selection of display screen..........................................................................................335 g.3 setting of synchronous signal ......................................................................................336 g.4 setting and changing register values related to display control ..................................340 g.4.1 setting of color palette....................................................................................340 g.4.2 switching procedure of synchronous mode .....................................................340 g.5 use of cursor display ..................................................................................................340 appendix h example of drawing control......................................................342 h.1 example of starting drawing .......................................................................................342 h.2 example of frame change by internal updating...........................................................342 h.3 using example of draw commands.............................................................................345 h.3.1 drawing polygons ...........................................................................................345 h.3.2 drawing optional shapes ................................................................................345 h.3.3 drawing circles and ellipses ...........................................................................345 h.3.4 drawing using source data..............................................................................345 h.3.5 expressing 3d space .......................................................................................346 h.4 special notes on using draw commands.....................................................................347 h.4.1 notes on the relationship of local offset and current pointer .........................347 h.4.2 notes on using relative-series commands......................................................347 h.4.3 notes on using source data ............................................................................348 h.5 functions to support drawing processing .....................................................................349 h.5.1 suspension/resumption of drawing.................................................................349 appendix i drawing performance ..................................................................351 appendix j usage of video capture function................................................354 j.1 example of video capture settings ..............................................................................354 j.1.1 example of interlace composite capture .............................................................354 j.1.2 example of modifying video data size...............................................................355 j.2 example of usage of captured data .............................................................................358 j.2.1 when displaying captured data on realtime video screen .................................358 j.2.2 when handling captured data as multi-valued source data ...............................358 j.3 video decoder .............................................................................................................36 3 j.3.1 field control by video decoder ..........................................................................363 rev. 2.0, 09/02, page xii of xviii j.3.2 video decoder settings....................................................................................... 364 appendix k product lineup .......................................................................... 366 rev. 2.0, 09/02, page xiii of xviii figures section 1 overview figure 1.1 sample system configuration ...................................................................................1 figure 1.2 reduced system size through use of ugm architecture..........................................2 figure 1.3 unified system bus interface ....................................................................................3 figure 1.4 double-buffering architecture..................................................................................4 figure 1.5 graphics accelerator .................................................................................................5 figure 1.6 pipeline graphics processing ....................................................................................5 figure 1.7 display composite function .....................................................................................6 figure 1.8 digital video images .............................................................................................. ..6 figure 1.9 data flow when using a 3d algorithm.....................................................................7 figure 1.10 internal block diagram .........................................................................................12 figure 1.11 state transition diagram.......................................................................................13 section 2 pins figure 2.1 pin configuration................................................................................................. ...15 figure 2.2 pin arrangement................................................................................................... ..16 figure 2.3 example of circuit for connection of pins cap1 and cap2....................................24 figure 2.4 connections of bypass capacitors between power supplies near the pins ...............25 figure 2.5 example of circuit for connection of rext, cbu, and cbl pins ..........................30 figure 2.6 example of connection of video input pins ............................................................31 section 3 ugm architecture figure 3.1 example of system configuration using ugm .......................................................34 figure 3.2 example of ugm mapping onto cpu memory space .............................................34 figure 3.3 byte exchange diagram..........................................................................................40 figure 3.4 image data specifications.......................................................................................41 figure 3.5 register setting procedure for d yuv/yuv-to-rgb conversion.............................41 figure 3.6 example of settings for transferring 320 240 yuv source data to ugm by means of four dma operations .........................................................................42 figure 3.7 configuration of one memory unit (512 bytes) ......................................................52 figure 3.8 ugm address transitions.......................................................................................53 figure 3.9 correspondence between ugm physical addresses (bytes) and 2-dimensinal virtual addresses .................................................................................................. .54 figure 3.10 work address space .............................................................................................55 figure 3.11 relationship between ugm physical addresses (byte) and work addresses .........55 figure 3.12 sample memory map (corresponding to 640 480 screen size, with 16 bits/pixel ) ...............................57 figure 3.13 relationship between 8-bits/pixel and 16-bits/pixel memory maps .......................58 figure 3.14 example of frame buffer fb1 location when hdis = 1 ......................................59 figure 3.15 screen coordinates ............................................................................................... 60 figure 3.16 rendering coordinates..........................................................................................62 rev. 2.0, 09/02, page xiv of xviii figure 3.17 multi-valued source coordinates (lni = 0) ..........................................................64 figure 3.18 multi-valued source coordinates with lni = 1 specified (linear address)...........64 figure 3.19 binary source coordinates....................................................................................65 figure 3.20 work coordinates................................................................................................. 66 figure 3.21 operation in auto display change mode ..............................................................69 figure 3.22 operation in auto rendering mode.......................................................................70 figure 3.23 operation in manual display change mode ..........................................................72 figure 3.24 operation when using vbkem command ...........................................................73 figure 3.25 display timing................................................................................................... ..75 figure 3.26 configuration of the display screen for q2sd ......................................................78 figure 3.27 example of background screen simple scroll (wrap = 0)...................................80 figure 3.28 example of background screen wraparound scroll (wrap = 1) ..........................81 figure 3.29 examples of raster scan control display..............................................................82 figure 3.30 display by interlace sync method.........................................................................84 figure 3.31 display by non-interlace method ..........................................................................85 figure 3.32 non-interlace mode display output......................................................................86 figure 3.33 interlace mode display output..............................................................................87 figure 3.34 (1) interlace sync & video mode output ..............................................................88 figure 3.34 (2) interlace sync & video mode output ..............................................................89 figure 3.35 signal flow in tv sync mode ..............................................................................91 figure 3.36 display timing................................................................................................... ..93 figure 3.37 &6<1& output waveform....................................................................................94 figure 3.38 drawing functions................................................................................................ 98 figure 3.39 example of polygon4 transfer data combinations ..........................................99 figure 3.40 multi-valued source data configuration ............................................................ 100 figure 3.41 example of kanji font as binary source (tdx = 24, tdy = 24)......................... 100 figure 3.42 binary work data configuration......................................................................... 101 figure 3.43 rendering attribute bit arrangement.................................................................. 102 figure 3.44 example of source style specification ................................................................ 103 figure 3.45 example of clipping specification ...................................................................... 104 figure 3.46 examples of even/odd select specifications....................................................... 105 figure 3.47 examples of bold line drawing ......................................................................... 107 figure 3.48 example of display list...................................................................................... 111 figure 3.49 example of timing for suspending and resuming background screen drawing.. 112 figure 3.50 updating of q2sds internal buffers................................................................... 113 figure 3.51 video incorporation signals................................................................................ 115 figure 3.52 video capture timing ........................................................................................ 115 figure 3.53 capture state .................................................................................................... .. 116 figure 3.54 display state.................................................................................................... ... 116 figure 3.55 video screen area .............................................................................................. 11 8 figure 3.56 interlace capture................................................................................................ . 119 figure 3.57 interlace composite capture ............................................................................... 119 figure 3.58 interlace capture (odd field).............................................................................. 120 rev. 2.0, 09/02, page xv of xviii figure 3.59 interlace capture (even field).............................................................................120 figure 3.60 interlace video input field handling specification ..............................................121 figure 3.61 reducing the size of the captured image.............................................................122 figure 3.62 incorrect settings for the reduction ratios ..........................................................123 figure 3.63 setting up the capture area.................................................................................124 figure 3.64 example of the settings for capture areas...........................................................125 figure 3.65 the flow of ycbcr (4:2:2) data .........................................................................126 figure 3.66 ycbcr (4:2:2) data format.................................................................................127 figure 3.67 conversion of ycbcr data into rgb format ......................................................128 figure 3.68 the rgb data format (16 bits/pixel) .................................................................128 figure 3.69 position of the video image ................................................................................129 figure 3.70 the display of data captured in interlace mode and display ..............................130 figure 3.71 the display of data captured in the interlace composite mode...........................131 figure 3.72 the display of data captured in the interlace odd-only mode ...........................132 figure 3.73 the display of data captured in the interlace even-only mode...........................133 section 6 usage notes figure 6.1 power-on sequence..............................................................................................269 figure 6.2 video interface timing .........................................................................................272 section 7 electrical characteristics figure 7.1 basis of v ol timing testing .................................................................................276 figure 7.2 test load circuit ................................................................................................. .277 figure 7.3 input clocks...................................................................................................... ....288 figure 7.4 reset timing ...................................................................................................... ..288 figure 7.5 cpu read cycle timing (cpu ? q2sd) with hardware wait .............................289 figure 7.6 cpu read cycle timing (cpu ? q2sd) with hardware wait .............................290 figure 7.7 (1) dma write cycle timing (single address, dmac ? q2sd) ........................291 figure 7.7 (2) dma write cycle timing (single address, dmac ? q2sd) ........................292 figure 7.7 (3) dma write cycle timing (dual address, dmac ? q2sd)...........................293 figure 7.7 (4) dma write cycle timing (dual address, dmac ? q2sd)...........................294 figure 7.8 interrupt output timing ........................................................................................295 figure 7.9 ugm read cycle timing .....................................................................................296 figure 7.10 ugm write cycle timing...................................................................................297 figure 7.11 (1) ugm refresh cycle timing ..........................................................................298 figure 7.11 (2) ugm mode register setting cycle timing....................................................299 figure 7.12 master mode display timing..............................................................................300 figure 7.13 (1) tv sync mode display timing .....................................................................301 figure 7.13 (2) tv sync mode display timing .....................................................................302 figure 7.14 (1) video interface timing..................................................................................303 figure 7.14 (2) video interface timing..................................................................................303 appendix c drawing algorithms figure c.1 two representations of a straight line on a raster display..................................316 rev. 2.0, 09/02, page xvi of xviii figure c.2 comparison of (a) 8-point drawing and (b) 4-point drawing................................ 317 figure c.3 drawing dot determination process in (a) 8-point drawing and (b) 4-point drawing ............................................................................................. 317 appendix d package dimensions figure d.1 package dimensions (fp-176) .............................................................................. 319 appendix f example of system configuration for superh figure f.1 example of system configuration overview......................................................... 326 figure f.2 example of interface timing ................................................................................ 327 figure f.3 example of memory mapping (using sh7709) .................................................... 329 figure f.4 ugm memory map.............................................................................................. 331 figure f.5 ugm address transition overview...................................................................... 332 appendix g example of display control figure g.1 example of display timing ................................................................................. 334 figure g.2 example of display timing under non-interlace mode ........................................ 336 figure g.3 example of display timing under interlace sink & video mode .......................... 338 figure g.4 cursor allocation................................................................................................. 341 appendix h example of drawing control figure h.1 display/drawing control timing chart (dbf = 0) ............................................... 344 figure h.2 example of referencing and branching................................................................ 346 appendix i drawing performance figure i.1 polygon4c drawing performance when fst = 0 (drawing range: 320 (h) 240 (v))...................................................................... 351 figure i.2 polygon4c drawing performance when fst = 1 (drawing range: 320 (h) 240 (v))...................................................................... 352 figure i.3 polygon4c drawing performance when fst = 0 (drawing range: 320 (h) 240 (v))...................................................................... 353 appendix j usage of video capture function figure j.1 interlace composite capture.................................................................................. 355 figure j.2 interlace composite capture (horizontal and vertical reduction ratios = 1/4) ...... 357 figure j.3 example of video data usage............................................................................... 359 figure j.4 q2sd video setting flow (1)................................................................................ 360 figure j.5 q2sd video setting flow (2)................................................................................ 361 figure j.6 q2sd video setting flow (3)................................................................................ 362 figure j.7 example of connection of video capture circuit .................................................. 363 figure j.8 example of interlaced data output timing for decoder......................................... 364 rev. 2.0, 09/02, page xvii of xviii tables section 1 overview table 1.1 a list of specifications ............................................................................................9 table 1.2 pin states after reset .............................................................................................14 section 2 pins table 2.1 pin functions ......................................................................................................... 17 table 2.2 operating mode selection ......................................................................................23 table 2.3 input clocks and operating frequencies .................................................................24 section 3 ugm architecture table 3.1 registers with internal update function..................................................................38 table 3.2 interrupt output function .......................................................................................51 table 3.3 setting for number of refreshes.............................................................................74 table 3.4 sample estimations of number of refresh cycles...................................................74 table 3.5 variables defined by display screen ......................................................................76 table 3.6 register settings..................................................................................................... 77 table 3.7 background screen related register settings .........................................................80 table 3.8 combinations of q2sd output and monitor input methods ....................................85 table 3.9 drawing commands...............................................................................................96 table 3.10 bold line drawing settings ..............................................................................106 table 3.11 8-bit pixel interface..........................................................................................126 table 3.12 selecting modes of video capture and display for the q2sd ...........................134 section 4 display list table 4.1 command list......................................................................................................137 section 5 registers table 5.1 registers ............................................................................................................. .199 table 5.2 bit configuration..................................................................................................226 table 5.3 yuv mode setting...............................................................................................229 table 5.4 video incorporation reduction ratio....................................................................233 appendix g example of display control table g.1 setting example of variables ((tvm1,0) = (0,0), (scm1,0) = (0,0)) .................337 table g.2 register setting example ((tvm1,0) = (0,0), (scm1,0) = (0,0)) .......................337 table g.3 setting example of variables ((tvm1,0) = (0,0), (scm1,0) = (1,1)) .................339 table g.4 register setting example ((tvm1,0) = (0,0), (scm1,0) = (1,1)) .......................339 appendix h example of drawing control table h.1 relationship of dbf and display screen (fg) ..................................................342 rev. 2.0, 09/02, page xviii of xviii rev. 2.0, 09/02, page 1 of 366 section 1 overview the q2sd (quick 2d graphics renderer with synchronous dram interface) is a 2d graphics renderer that supports sdram interface in the sh microcomputer graphics accelerator quick series (q series), based on the concepts of simplicity, realtime operation, and upgradability. the use of unified graphics memory (ugm), a double-buffering sys tem that switches drawing and display buffers in frame units, and the video-input function, providing a high-speed drawing performance of 60 screens per second, has made possible minimization of graphics memory (with the minimum configuration of a single 16-mbit sdram memory), unified handling of graphics and natural images, and realtime software 3d graphics drawing. the separation of geometric operations (handled by the cpu) and rendering operations (handled by the q2sd) has also resulted in improved system bus utilization. the q2sd is a high-performance graphics rendering lsi for multimedia applications, which provides both drawing and display, video input functions integrated into a single chip. a sample q2sd system configuration is shown in figure 1.1. 400 240, etc. analog rgb video decoder video encoder analog ntsc analog rgb video amplifier display monitor q2sd superh or cpu memory data (16 or 32) data (16) data (16) address (14) address control external video ugm (sdram) note: 16-bit/8-bit color precision binary/multi-valued source binary work area frame buffer 0* frame buffer 1* display list cursor video screen background screen * digital video data (8) figure 1.1 sample system configuration rev. 2.0, 09/02, page 2 of 366 1.1 features simple (optimized system configuration): (1) use of unified graphics memory (ugm) architecture unified handling of image data (unified graphics memory ( ugm) arch itecture) data in various formats can be stored and managed in the same unified graphics memory (see figure 1.2). minimum necessary ugm minimum ugm configur ation: one 16-bit-data-bus type 16-mbit synchronous dram monochrome font (binary source) color (multi-valued source) 8 bits/pixel 16 bits/pixel monochrome pattern (binary work area) polygon... display list (16-bit instructions) minimum configuration: 16-mbit sdram foreground screen (double buffer) background screen video screen cursor (2 pcs) 16m sdram quick quick 2d menu g figure 1.2 reduced system size through use of ugm architecture rev. 2.0, 09/02, page 3 of 366 allocating the ugm in the cpus memory space a cpu interface circuit is incorporated to provide a unified interface. the ugm is allocated in the cpus memory space (see figure 1.3). this simplifies the ugm manag ement by the cpu. ugm (u nified g raphics m emory ) frame buffer 0 display list frame buffer 1 binary work area binary/multi-valued source the cpu can access the ugm directly via the q2sd sdram 2sd figure 1.3 unified system bus interface rev. 2.0, 09/02, page 4 of 366 realtime: (1) use of double-buffering architecture the use of a double-buffering architecture that allows switching between the drawing buffer and display buffer in frame or field units enables realtime operation by synchronous with display processing with high-speed drawing processing (see figure 1.4). frame buffer (dispalying) frame buffer (drawing) double-buffer control drawing displaying monitor switching buffers frame buffer (displaying) double-buffer control drawing displaying frame buffer (drawing) monitor quick quick 2d quick quick 2d quick quick 2d quick quick 2d quick quick 2d quick quick 2d quick quick 2d quick quick 2d quick quick 2d quick quick 2d quick quick 2d quick quick 2d quick quick 2d quick quick 2d quick quick 2d quick quick 2d quick quick 2d quick quick 2d figure 1.4 double-buffering architecture rev. 2.0, 09/02, page 5 of 366 (2) graphics accelerator a dedicated hardware is used for the inefficient processing in the cpu. thus, cpu bus efficiency is improved and high-speed realtime drawing is realized (see figure 1.5). sd sd 2 2 rendering operation control superh risc engine geometric operation coordinates operation cpu bus efficiency is improved by using q2sd for all rendering processing high-speed realtime drawing dedicated hardware is used for insufficient processing in cpu making display list by cpu drawing in ugm according to display list by q2sd figure 1.5 graphics accelerator (3) pipeline graphics processing: high-speed graphics processing is enabled by pipelining the cpu geometry processing and q2sd rendering processing (see figure 1.6). geometry 1 rendering 1 geometry 2 rendering 2 geometry 3 rendering 3 geometry 1 geometry 2 geometry 3 rendering 1 rendering 2 rendering 3 cpu cpu q2sd processing time figure 1.6 pipeline graphics processing (4) use of write-only drawing: write-only drawing (a drawing method using only write operations) is used to improve drawing performance. rev. 2.0, 09/02, page 6 of 366 (5) display composite function the drawing time can be reduced by changing only the images that have been modified (see figure 1.7). cursor screen video screen background screen display foreground screen menu menu display composite figure 1.7 display composite function (6) digital video capture realtime expression of digital video images in various types can be achieved. (2) two-screen display (3) pinp display 8 bits/pixel (4) multi-screen display (1) full-screen display video display 16 bits/pixel (yc format) graphics display (16 bits/pixel) (rgb format) digital video data in ycbcr 4:2:2 format is stored in the ugm with or without reduction. it is displayed on the video screen. digital video data in ycbcr 4:2:2 format is converted to the rgb565 format and is stored in the ugm. using it as a source data, still picture is drawn in 16 bits/pixel mode. (1) to (3): (4): @ ? @ ? @ @ ? ? @ @ ? ? figure 1.8 digital video images rev. 2.0, 09/02, page 7 of 366 (7) support for sdram sdram can be used for the ugm. this enables the q2sd to use burst access to the ugm and perform high-speed drawing. upgradability: (1) algorithm upgrading in the q2sds drawing system, algorithms for coordinate conversion, etc., are executed by the cpu, using a systematized data base containing coordinates and other data, and the results are represented in graphical form. thus, the graphics for a variety of shapes can be implemented simply by upgrading the algorithms, without having to modify the data base (see figure 1.9). 3d algorithm (software) data base (coordinate vertices, etc.) display list drawing by q2sd drawn figure quick quick 2d quick quick 2d quick quick 2d figure 1.9 data flow when using a 3d algorithm (2) drawing system upgrading the q2sd has been developed as a member of the q series, enabling the user to select the most appropriate model from the series for a particular application. the users drawing system can also be upgraded as necessary by changing the q2sd or cpu combination. rev. 2.0, 09/02, page 8 of 366 (3) consistency of app lication interface the q2sds carefully selected drawing commands are of four kinds: four-vertex screen drawing, line drawing, work screen drawing, and work line drawing. this makes it possible to reduce the parts dependent upon drawing commands within an application, and so achieve a more consistent interface between applications. rev. 2.0, 09/02, page 9 of 366 1.2 a list of specifications table 1.1 summarizes the specifications of the q2sd. table 1.1 a list of specifications item function/performance drawing drawing performance polygon drawing performance (20 25 pixels): 91,000/sec (2-screen composite mode: 60,000/sec) line drawing performance (10 pixels): 1,200,000/sec (2-screen composite mode: 400,000/sec) color representation source: 1/8/16 bits/pixel; drawing: 8/16 bits/pixel; work: binary drawing commands 4-vertex screen drawing, line drawing, work screen drawing, work line drawing register setting commands current pointer setting, local offset setting, clipping, specific address-mapped register setting sequence control commands jump, subroutine, vertical blanking interval wait, no operation, display list end display functions sample screen sizes 320 240, 400 240, 480 240, 640 480, ntsc, pal, etc. crt scanning system non-interlace, interlace, interlace sync & video external synchronization master, tv synchronization color palette simultaneous display of 256 colors out of 260,000 cursors two cursors, 32 32 pixels, display color selectable from color palette display screen foreground, background, and video screens video input 8-bit multiplexed ycbcr 4:2:2 digital input system drawing system internal operation maximum clock frequency (q2sd operating frequency) 66 mhz 1, 33 mhz 2, 16.5 mhz 4 (using multiplier) display system internal operation clock frequency (display operation clock frequency) operating frequency/2 (max. 33 mhz) rev. 2.0, 09/02, page 10 of 366 table 1.1 summary of q2sd functions (cont) item function/performance system sh inter- face command/ data transfer dma transfer (single address, dual address), or performed by superh yuv ? rgb conversion 16-bit input, 4:2:2 (8 bits each for y, u, v) 16-bit output (r: 5, g: 6, b: 5 bits) d yuv ? rgb conversion 8-bit input (4 bits each for d-y, d-u, d-v) 16-bit output (r: 5, g: 6, b: 5 bits) interrupt output tv sync signal error flag, frame flag, dma flag, command error flag, vertical blanking flag, trap flag, command suspend flag, drawing break flag superh supported can be allocated to the sram area of the superh with 3.3-v power supply. ugm interface 32/16-bit- bus-width sdram minimum 16 mbits (choice of one 16-mbit ( 16) memory, two parallel 16-mbit ( 16) memories, one 64- mbit ( 16) memory, or one 64-mbit ( 32) memory) dac analog rgb output 6-bit resolution for each of r, g, and b (8-bit resolution for each of r, g, and b for video stored in ugm in ycbcr format) process/package 0.35- m cmos/176-pin lqfp power supply voltage/temperature range 3.3 v 0.3 v/0 c to 70c (details of a - 40c to 85c special-specification model are also available from hitachi sales representatives) 1.3 block diagram figure 1.10 shows a block diagram of the q2sd. the functions of the various blocks in figure 1.10 are as follows. cpu interface unit performs ugm access by the cpu, q2sd on-chip register accesses by the cpu, and ugm write access by the external dmac. converts input d ata d yuv (260,000 colors) or yuv (260,000 colors) to rgb data (60,000 colors), and stores it in the ugm. interrupts are output. ugm interf ace unit controls the connection relating to the sdram that is used for the ugm. chip manager controls the operation of each unit in the ugm arch itecture. rev. 2.0, 09/02, page 11 of 366 clock generator (cpg0, cpg1) the q2sd operating clock is generated in the cpg0, and it is provided to each unit excluding the display unit. the display dot clock is generated in the cpg1 and it is provided to the display unit. rendering unit performs fetching and interpretation of the display list in the ugm. rendering buffer unit buffers data and addresses between the rendering unit and the ugm to improve the efficiency to the ugm access in the rendering unit. display unit generates the crt control signals and outputs analog rgb signals. display buffer unit composes the foreground, background, video and cursor screens. accesses data to be displayed in synchronization with the display timing. by the color palette (6 bits per color), converts 8-bits/pixel data to display data of 256 colors out of 262,144 to the rgb data, based on the color conversion table, and when the video screen data is the ycbcr data, it is converted to the rgb data. video-in unit fetches 4:2:2 ycbcr data and stores it in the ugm in ycbcr or rgb for mat. the image data can also be stored with reduction. rev. 2.0, 09/02, page 12 of 366 clk1 clk0 cpg1 display unit rendering unit rendering buffer unit video-in unit cpu data bus dma control cpu address bus ugm data bus ugm address bus color palette display buffer unit dac cpg0 i/o buffer ugm interface unit chip manager cpu interface unit yuv ? rgb conversion d yuv ? rgb conversion i/o buffer i/o buffer i/o buffer figure 1.10 internal block diagram rev. 2.0, 09/02, page 13 of 366 1.4 processing states the q2sd has five main processing states: the power-on state, initial state, reset state, ugm initialization state, and normal states. figure 1.11 shows the state transitions. power-on initial state (reset) = low (reset) = low (reset release) mode 2 to 0 = b'000, b'001, b'010 = high reset state normal state (reset) = low ugm initialization state figure 1.11 state transition diagram 1.4.1 power on for details, refer to section 6.1, power-on sequence. 1.4.2 initial states (when specified power is supp lied) initial states are undefined. registers: undefined i/o pins: undefined output pins: low/high-level output rev. 2.0, 09/02, page 14 of 366 1.4.3 reset state (when low level is input to 5(6(7 5(6(7 pin) table 1.2 shows the q2sd pin states immediately after a reset. ugm refreshing is not performed when the 5(6(7 pin is low. the levels of pins mode2 to mode0 are latched at the rising edge of the 5(6(7 pin. at this time, they must be fixed at a level of b 000, b 001, or b 010. other levels must not be used because those setting makes the q2sd enter in test mode. table 1.2 pin states after reset i/o pins input state d0 to d15 * , 96<1& / (;96<1& , +6<1& / (;+6<1& , 2'') output state (low-level output) md0 to md31 output pins low-level output disp, cde high-level output '5(4 , ,5/ , :$,7 low/high-level output &6<1& , ma0 to ma13, 0:( , 05$6 , 0&$6 , ldqm0, ldqm1, udqm0, udqm1, mclk note: pins d0 to d15 are in the output state when 5' is a low-level input. 1.4.4 ugm initialization state initializes the sdram which is used for the ugm. for d etails on initialization, refer to section 6.6, sdram mode register values for ugm set by q2sd. 1.4.5 normal operating state in the normal operating state, the q2sd executes drawing commands and performs display control. rev. 2.0, 09/02, page 15 of 366 section 2 pins 2.1 pin configuration figure 2.1 shows an overview of the q2sds pins. unused input pins should be made inactive by pulling them up or down. system control (8) cpu interface (47) power supply (42) power supplies for q2sd buffers are divided into the following groups. power supply group 1: for pll (2) power supply group 2: for dac (6) power supply group 3: general-purpose (34) (lqfp176) q2sd q2sd pin arrangement signals: 129 pins capacitance: 4 pins reference: 1 pin power supply: 42 pins display interface (12) video input interface (12) ugm interface (54) mode0 to mode2 clk0 clk1 cap1 gnd a1 to a22 22 16 pllvcc d0 to d15 pllgnd dacvcc dacgnd vcc cbu vin0 to vin7 vqclk r,g,b cbl rext / / disp cde ldqm0 ldqm1 udqm0 mclk ma0 to ma13 md0 to md31 cap2 3 32 14 8 3 3 3 15 19 udqm1 (also functions as ma13) figure 2.1 pin configuration rev. 2.0, 09/02, page 16 of 366 2.2 pin arrangement figure 2.2 shows the pin arrangement of the q2sd. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 d4 d5 vcc d6 gnd d7 d8 d9 d10 d11 d12 vcc d13 gnd d14 d15 gnd a1 a2 a3 a4 a5 a6 a7 vcc a8 gnd a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 vcc a19 gnd a20 a21 a22 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 ma9 ma10 ma11 ma12 gnd udqm1/ma13 vcc udqm0 ldqm1 ldqm0 md8 gnd mmd9 vcc md10 md11 md12 md13 md14 md15 gnd md7 vcc md6 md5 gnd md4 md3 gnd md2 vcc md1 md0 pllgnd cap2 cap1 pllvcc mclk clk0 mode2 mode1 mode0 vin7 vin6 vin5 vin4 vin3 vin2 vin1 vin0 md31 md30 md29 md28 gnd md27 vcc md26 md25 gnd md24 md16 md17 gnd md18 vcc md19 md20 md21 md22 md23 ma0 gnd ma1 vcc ma2 ma3 ma4 ma5 gnd ma6 vcc ma7 ma8 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 nc vqclk clk1 vcc / gnd / dacgnd dacvcc r g dacvcc b dacgnd cbu cbl rext dacvcc dacgnd gnd vcc disp gnd cde vcc gnd d0 d1 d2 d3 lqfp 176 (top view) figure 2.2 pin arrangement rev. 2.0, 09/02, page 17 of 366 2.3 pin functions table 2.1 shows the q2sd pin functions. table 2.1 pin functions type symbol pin no. i/o function system control mode0 45 input operating mode pin 0 mode1 46 input operating mode pin 1 mode2 47 input operating mode pin 2 clk0 48 input q2sd operating clock clk1 138 input display operating clock 5(6(7 44 input reset cap1 51 output multiplication circuit external capacitance pin cap2 52 output multiplication circuit external capacitance pin cpu interface a1 18 input cpu address 1 a2 19 input cpu address 2 a3 20 input cpu address 3 a4 21 input cpu address 4 a5 22 input cpu address 5 a6 23 input cpu address 6 a7 24 input cpu address 7 a8 26 input cpu address 8 a9 28 input cpu address 9 a10 29 input cpu address 10 a11 30 input cpu address 11 a12 31 input cpu address 12 a13 32 input cpu address 13 a14 33 input cpu address 14 a15 34 input cpu address 15 a16 35 input cpu address 16 a17 36 input cpu address 17 a18 37 input cpu address 18 a19 39 input cpu address 19 a20 41 input cpu address 20 rev. 2.0, 09/02, page 18 of 366 table 2.1 pin functions (cont) type symbol pin no. i/o function cpu interface a21 42 input cpu address 21 a22 43 input cpu address 22 d0 173 i/o cpu data 0 d1 174 i/o cpu data 1 d2 175 i/o cpu data 2 d3 176 i/o cpu data 3 d4 1 i/o cpu data 4 d5 2 i/o cpu data 5 d6 4 i/o cpu data 6 d7 6 i/o cpu data 7 d8 7 i/o cpu data 8 d9 8 i/o cpu data 9 d10 9 i/o cpu data 10 d11 10 i/o cpu data 11 d12 11 i/o cpu data 12 d13 13 i/o cpu data 13 d14 15 i/o cpu data 14 d15 16 i/o cpu data 15 &6 162 input chip select 0 (ugm) &6 163 input chip select 1 (internal registers) 5' 164 input read strobe :( 165 input write pulse 0 (lower) :( 166 input write pulse 1 (upper) '$&. 167 input dma acknowledge '5(4 168 output dma request :$,7 169 output cpu wait ,5/ 171 output interrupt request display interface cbu 150 output dac external capacitance pin cbl 151 output dac external capacitance pin rext 152 output dac external reference pin r 145 output display data analog output r rev. 2.0, 09/02, page 19 of 366 table 2.1 pin functions (cont) type symbol pin no. i/o function display interface g 146 output display data analog output g b 148 output display data analog output b &6<1& 157 output composite sync output signal +6<1& / (;+6<1& 140 i/o horizontal sync output/external horizontal sync input 96<1& / (;96<1& 142 i/o vertical sync output/external vertical sync input disp 159 output signal indicating display period (high during display period) cde 161 output color detection (high in case of specific color output) 2'') 155 i/o signal indicating odd field (low when odd) video input vin0 125 input video input data 0 interface vin1 126 input video input data 1 vin2 127 input video input data 2 vin3 128 input video input data 3 vin4 129 input video input data 4 vin5 130 input video input data 5 vin6 131 input video input data 6 vin7 132 input video input data 7 9+6 134 input video horizontal sync input 996 135 input video vertical sync input 92'' 136 input signal indicating video input odd field vqclk 137 input video input valid data capture clock ugm interface ma0 103 output memory address 0 ma1 101 output memory address 1 ma2 99 output memory address 2 ma3 98 output memory address 3 ma4 95 output memory address 4 ma5 94 output memory address 5 ma6 92 output memory address 6 ma7 90 output memory address 7 rev. 2.0, 09/02, page 20 of 366 table 2.1 pin functions (cont) type symbol pin no. i/o function ugm interface ma8 89 output memory address 8 ma9 88 output memory address 9 ma10 87 output memory address 10 ma11 86 output memory address 11 ma12 85 output memory address 12 ma13 83 output memory address 13 (also functions as udqm1) md0 54 i/o memory data 0 md1 55 i/o memory data 1 md2 57 i/o memory data 2 md3 59 i/o memory data 3 md4 60 i/o memory data 4 md5 62 i/o memory data 5 md6 63 i/o memory data 6 md7 65 i/o memory data 7 md8 76 i/o memory data 8 md9 74 i/o memory data 9 md10 72 i/o memory data 10 md11 71 i/o memory data 11 md12 70 i/o memory data 12 md13 69 i/o memory data 13 md14 68 i/o memory data 14 md15 67 i/o memory data 15 md16 113 i/o memory data 16 md17 112 i/o memory data 17 md18 110 i/o memory data 18 md19 108 i/o memory data 19 md20 107 i/o memory data 20 md21 106 i/o memory data 21 md22 105 i/o memory data 22 md23 104 i/o memory data 23 md24 114 i/o memory data 24 rev. 2.0, 09/02, page 21 of 366 table 2.1 pin functions (cont) type symbol pin no. i/o function ugm interface md25 116 i/o memory data 25 md26 117 i/o memory data 26 md27 119 i/o memory data 27 md28 121 i/o memory data 28 md29 122 i/o memory data 29 md30 123 i/o memory data 30 md31 124 i/o memory data 31 0&6 77 output memory chip select 0:( 78 output memory write pulse 05$6 96 output row select signal 0&$6 97 output column select signal ldqm0 79 output lower word, lower byte i/o mask ldqm1 80 output lower word, upper byte i/o mask udqm0 81 output upper word, lower byte i/o mask udqm1 83 output upper word, upper byte i/o mask (also functions as ma13) mclk 49 output memory clock power supply vcc 3 power supply buffer/internal vdd vcc 12 power supply buffer/internal vdd vcc 25 power supply buffer/internal vdd vcc 38 power supply buffer/internal vdd vcc 56 power supply buffer/internal vdd vcc 64 power supply buffer/internal vdd vcc 73 power supply buffer/internal vdd vcc 82 power supply buffer/internal vdd vcc 91 power supply buffer/internal vdd vcc 100 power supply buffer/internal vdd vcc 109 power supply buffer/internal vdd vcc 118 power supply buffer/internal vdd vcc 139 power supply buffer/internal vdd vcc 158 power supply buffer/internal vdd vcc 170 power supply buffer/internal vdd rev. 2.0, 09/02, page 22 of 366 table 2.1 pin functions (cont) type symbol pin no. i/o function power supply gnd 5 ground buffer vss gnd 14 ground buffer vss gnd 27 ground buffer vss gnd 40 ground buffer vss gnd 58 ground buffer vss gnd 66 ground buffer vss gnd 75 ground buffer vss gnd 84 ground buffer vss gnd 93 ground buffer vss gnd 102 ground buffer vss gnd 111 ground buffer vss gnd 120 ground buffer vss gnd 141 ground buffer vss gnd 160 ground buffer vss gnd 172 ground buffer vss gnd 17 ground internal vss gnd 61 ground internal vss gnd 115 ground internal vss gnd 156 ground internal vss pll vcc 50 power supply multiplication circuit vdd pll gnd 53 ground multiplication circuit vss dac vcc 144 power supply dac vdd dac vcc 147 power supply dac vdd dac vcc 153 power supply dac vdd dac gnd 143 ground dac vss dac gnd 149 ground dac vss dac gnd 154 ground dac vss other nc 133 no-connection (should be open.) rev. 2.0, 09/02, page 23 of 366 2.4 system control pins 2.4.1 operating mode pins ? mode0, mode1, and mode2 these pins control the q2sds operating mode. the mode is fixed in a reset-startup and cannot be changed after reset. table 2.2 operating mode selection mode2 mode1 mode0 description l l l normal operation state. multiplication on. the external input clock is duty-free. the internal operating clock has the same frequency as the external input clock. l l h normal operation state. multiplication on. the external input clock is duty-free. the internal operating clock has twice the frequency of the external input clock. l h l normal operation state. multiplication on. the external input clock is duty-free. the internal operating clock has four times the frequency of the external input clock. l h h setting prohibited. h ** setting prohibited. legend h: high level l: low level * : either high or low level 2.4.2 clock pins ? clk0, clk 1, cap1, and cap2 there are two q2sd clocks, clk0 and clk1. the clock used as the base for the q2sd operating clock is input to the clk0 pin, and the clock used as the display operating clock is input to the clk1 pin. the q2sd operating clock is the base clock for q2sds operations, and is also used as the base clock for ugm access. the q2sd includes an operating clock multiplication circuit that enables a 1, 1/2, or 1/4 multiple of the operating clock to be selected for input to the clk0 pin. rev. 2.0, 09/02, page 24 of 366 the display operating clock is the base clock for display operations, and is used to control display dot clock, display data output and generate horizontal and vertical sync signals. the relationship between the clocks and operating frequencies is summarized in table 2.3. table 2.3 input clocks and operating frequencies clock input pin clock type input clock clk0 one of the clocks on the right is the q2sd operating clock. clock with the clk0 frequency, and duty cycle adjusted to 50% clock with twice the clk0 frequency, and duty cycle adjusted to 50% clock with four times the clk0 frequency, and duty cycle adjusted to 50% clk1 the clock on the right is the display operating clock. clock with the clk1 frequency the q2sd operating clock and display operating clock frequencies can be set to any values within the following range. this enables to perform drawing at a maximum operating clock independently of the characteristics of the display device. q2sd operating clock 3 2 display operating clock (where display operating clock 33 mhz) cap1 and cap2 are external capacitance pins for the multiplication circuit. figure 2.3 shows an example circuit for connection of pins cap1 and cap2. the capacitor c0 and resistor r0 of the internal pll for oscillation settling must be placed near pins cap1 and cap2, and must not cross with other signals. the c0 ground must be provided from the pllgnd. c0 and r0 are an external capacitor and a noise-reduction resistor for a pll charge pump. q2sd pllvcc cap2 cpb = about 0.1 m f system power supply system ground cap1 pllgnd r0 = about 0 to 2 k w c0 = about 470 pf r0 = about 0 to 2 k w c0 = about 470 pf r0 = about 30 w r0 = about 30 w figure 2.3 example of circuit for connection of pins cap1 and cap2 rev. 2.0, 09/02, page 25 of 366 2.4.3 reset pin ? 5(6(7 a hardware reset signal is input to this pin. when the signal is at a low level, the q2sd enters the hardware reset state. at this time, pin states are initialized as shown in table 1.2 and register contents are also initialized. 2.4.4 power supply pin ? vcc, gnd, pllvcc, pllgnd, dacvcc, dacgnd the normal power supply, dac power supply, and pll power supply are connected to 3.3 v. there are several normal power supply and dac power supply pins and power must be supplied to all those pins. normal power supply (vcc, gnd), pll power supply (pllvcc, pllgnd), and dac power supply (dacvcc, dacgnd) must be separ ated from the boards power supply source, and bypass capacitors cpb, cb1, and cb2 must be inserted near the pins. since the dac outputs signals with high resolution, external noise should be reduced. it is recommended that at least one electrolytic capacitor should be placed each of between power supply and gnd pins other than cap acitors cpb, cb1, and cb2. it is also recommended that differences of voltage levels for each power supply pin should be reduced to avoid dacs latch- up and an inductance with about 100 m h or a noise filter should be inserted between the dacvcc and vcc pins to cut out high frequency noise. pllvcc rev. 2.0, 09/02, page 26 of 366 2.5 cpu interface pins ? a1 to a22, d0 to d15, &6 , &6 , 5' , :( , :( , '$&. , '5(4 , :$,7 , ,5/ 2.5.1 cpu writes the cpu can access the ugm or a q2sd internal registers. in a ugm access, a low-level signal is input to &6 ; in a q2sd internal register access, a low-level signal is input to &6 . &6 and &6 must not be driven low at the same time. the ugm or q2sd internal register address is input to a1 to a22. input the addresses of the ugm within the range sp ecified by the memory mode register (memr) to pins a1 to a22. route the wire so that pins a22 and a21 are fixed at low levels when a single memory of 16 mbits is in use and route the wire so that pin a22 is fixed at a low level when two memories of 16 mbits are in use. the address is a byte address. only word (2-byte) access can be used in the q2sd for registers, while word access or byte access can be used for the ugm. in word access, input a low-level signal to both :( and :( ; in byte access, drive :( low for an access to bits 7 to 0, or drive :( low for an access to bits 15 to 8. the q2sd uses the :$,7 signal to notify the cpu of a delay in cpu access due to an internal q2sd operation. however, because of the high-level width specification for the :( and :( signals, the cpu external bus operating frequency should be set equal to or lower than the q2sds internal operating frequency. following detection of a low level of &6 or &6 and a low level of 5' , :( , or :( , there is a maximum interval of 3 cycles, followed by an output buffer delay (max. 15 ns), before the q2sds :$,7 signal is asserted. the number of software waits should be adjusted by software according to the frequency ratio between the cpu and q2sd, and system specifications such as synchronous or asynchronous operation. in some superh risc engine family products, the &6 pin is initially set as an input port. if this signal is connected directly to the &6 or &6 signal of the q2sd, pull up the superhs &6 pin externally to prevent the voltage level from becoming unstable in a reset. when using a cpu that uses an 5'< signal for interfacing, invert the q2sds :$,7 signal and use it as the 5'< signal. the :$,7 signal is output for a minimum of 1 tcyc0 when accessing the q2sd. 2.5.2 cpu reads a read operation is basically the same as a write operation. reads are performed in word units. although write operations are indicated by signals :( and :( , read operations are indicated by the low level of the 5' signal. rev. 2.0, 09/02, page 27 of 366 2.5.3 dma writes the cpu can perform write dma access, using cycle stealing, to the ugm or a q2sd address- mapped register (the image data entry register (ide)). to perform dma access, dma transfer start address, dma transfer word count, and sys tem control register dma mode and dma address mode settings must be made. after the dma mode s ettings are made, the q2sd dives the '5(4 signal low as soon as its preparations are completed. when the dma contro ller receives this signal, it drives the '$&. signal low and begins dma access. dma access is performed in word units. use a dma mode s etting of b 01 (dma transfer to the ugm) when performing dma wr ites with a yuv mode (yuv2, yuv1, yuv0 in the input d ata conversion mode register (iemr)) setting of b 000, and a dma mode s etting of b 11 (dma transfer to the image data entry register (ider)) when performing dma wr ites with a yuv mode s etting other than b 000. when dma address mode bits daa1 and daa0 in the sys tem control register ( sysr) are is set to b 00 or b 01, transfer is performed using single address transfer timing. when the dma address mode (daa1, daa0) is set to b 10, transfer is performed using dual address transfer timing. in this case, access to the q2sd should be performed by driving '$&. low. &6 is ignored. the dma mode is set to b 01 for ugm access, and to b 11 for q2sd address-mapped register (image data entry register (ide)) access. other address-mapped registers cannot be accessed. the destination address ( ugm address) is set as the dma transfer start address (dmsarh, dmsarl), and the number of words set as the dma transfer word count (dmawrh, dmawrl) are transferred. the q2sd controls the ugm addresses using the on-chip address counter. addresses input from off-chip are not used. when making another dma mode s etting after dma transfer ends, first check that the dmf bit is set to 1 in the status register. in dma transfer from synchronous dram to the q2sd, the d0 to d15 setup time (t wrdrs ) relative to the rise of the 5' signal must be at least two q2sd system operating clock cycles, and therefore the external bus operating frequency must be no higher than 1/2 the system operating clock frequency. when using the dmac, make the following dmac s ettings. for dma transfer in dual address mode ? '$&. output in write cycle ? active-low '$&. output ? fixed destination address (set any ugm address) ? source address incremented ? external request, dual address mode ? '5(4 falling-edge detection rev. 2.0, 09/02, page 28 of 366 ? cycle stealing for dma transfer in single address mode ? '$&. output in read cycle ? active-low '$&. output ? fixed destination address ? source address incremented ? external request, single address mode ? '5(4 falling-edge detection ? cycle stealing the superh family includes models in which the initial dack pin setting is active-high. in this case, leave the dack pin at its initial setting (active-high) and use an external circuit to invert the dack pin signal before connection to the q2sds '$&. pin. 2.5.4 interrupts the q2sd requests interrupts to the cpu by means of internal sources. interrupt sources are set in the interrupt enable register (ier). 2.6 ugm interface pins ? ma0 to ma13, md0 to md31, 0&6 , 0:( , 05$6 , 0&$6 , ldqm0, ldqm1, udqm0, udqm1, mclk the q2sd allows synchronous dram to be used as the ugm, and has a dir ect interface for synchronous dram. when connecting only one synchronous dram with a data bit width of 16, use pins md0 to md15, and leave pins md16 to md31 open. the operating mode of the synchronous dram (write mode, &$6 latency, burst type, and burst length) is set automatically by the q2sd. for refreshing, auto-refresh mode is used. synchronous dram precharging is carried out using the precharge all banks (pall) command. 2.7 display interface pins the signals output from the display interface pins are all synchronized with the display operating clock. 2.7.1 display signal output ? r, g, b rgb analog display signals are output. the pixel data resolution is 6 bits for each of r, g, and b. outside the display period, the image data (r, g, b) goes to the level corresponding to h 000. rev. 2.0, 09/02, page 29 of 366 2.7.2 video encoder interface ? csync outputs the composite sync signal ( &6<1& ). in master mode, equalizing pulses can also be added to the composite sync signal. 2.7.3 crt interface ? hsync/ (;+6<1& , 96<1& / (;96<1& , disp, cde, 2'') inputs/outputs the horizontal and vertical sync signals to the hsync/ (;+6<1& and 96<1& / (;96<1& pins. inputs/outputs the signal indicating whether the current field is odd or even for interlace control to the 2'') pin. when the q2sd has a mastership for synchronization, these signals are outputs. when an external device (tv or vcr) has a mastership, these signals are inputs. since these signals are input during the reset state, they must be pulled up to fix the levels, meaning that the direction is a non-significant. the tv sync mode bits in the display mode register (bits tvm1 and tvm0 in dsmr) select either master (output) or tv sync (input). the cde pin outputs a high level when a specified color in a display area in the ugm is detected. cder specifies the color to be detected. display synthesis of external video and q2 graphics image in one pixel units is enabled by using the cde pin for selecting the external selection circuit for the external video or q2 graphics image. the disp signal indicates the display period in which the high level is output. 2.7.4 d/a converter ? cbu, cbl, and rext the d/a converter changes output levels linearly in accordance with the display data. connect the specified resistors or capacitors to the rext, cbu, and cbl pins. connect resistive load rl to the r, g, and b output pins. the relationship between ioutmax which is the maximum value of the output current iout and rext can be given in the following expression. rext = (2.842/iout) dacvcc. where vout is an amplitude when the current of ioutmax is flowing in the resistive load rl, rext can given in the following expression. rext = (2.842/(vout/rl)) dacvcc therefore, to obtain vout = 1 vpp when rl = 330 w and dacvcc = 3.3 v, rext = 3.1 k w . the range of maximum output current ioutmax must be set within the range from 2.0 ma to 3.0 ma. rev. 2.0, 09/02, page 30 of 366 the d/a converter has 8-bit resolution, but the dynamic settling error is determined by resistive load rl, output pin load c (total of routing and video amp input capacitances), and display operating frequency f. for example, when rl = 330 w , c = 20 pf, and f = 33 mhz, the value of n when the following equation is satisfied is the d/a converter accuracy. exp - 1 rl c f 1 2 n () (where n is an integer) since n is 6 in this case, the d/a converter has 6-bit accuracy. (the dynamic settling error is 1/2 6 = 1.56% full-scale.) i out rl = 330 w 75 w + C rl = 330 w rl = 330 w i out 75 w + C i out 75 w + C q2sd dacv cc cbu 0.1 m f 0.1 m f 3.1 k w power supply ground video amp analog rgb output cbl rext dacgnd r g b figure 2.5 example of circuit for connection of rext, cbu, and cbl pins 2.8 video interface pins ? vin0 to vin7, 9+6 , 996 , 92'' , vqclk 2.8.1 video input interface an 8-bit ycbcr 4:2:2 video data that is synchronous with the vqclk must be input to vin0 to vin7. input must be made to the vqclk only when there is a valid data in data pairs. a horizontal and vertical synchronous signals must be input to 9+6 and 996 . the start position of rev. 2.0, 09/02, page 31 of 366 the data fetching is determined by these signals. a signal indicating the video input field must be input to 92'' . a low-level signal indicates the odd field and a high-level signal indicates the even field. q2sd vhs vvs vodd vqclk vin7 to vin0 ntsc video decoder vsync hsync field vclk yin v data 7 to v data 0 28.6363 mhz clk 10 m f 75 w vin sample clock ntsc figure 2.6 example of connection of video input pins rev. 2.0, 09/02, page 32 of 366 rev. 2.0, 09/02, page 33 of 366 section 3 ugm architecture 3.1 features the unified graphics memory (ugm) conn ected to the q2sd is used for the following purposes. foreground (fg), background (bg), and cursor screen areas areas that perform drawing and displaying. double-buffering architecture (frame buffer 0: fb0, frame buffer 1: fb1) is used for the foreground screens. display list area area that stores the q2sd command list. the q2sd fetches commands from this area while carrying out drawing operations. work, source, and rendering areas, used as the work area that stores patterns for painting or cutting-out and is for drawing with ftrap command, as the binary source area that stores font data, as the multi-valued source area that stores natural images and icons, and as the rendering area that is specified by rsar. video area stores video data for three screens taken by the video capture function (the size of a single screen is a video-window size). others the ugm can be allocated to part of the cpus main memory area, enabling it to be used as cpu work areas as well as for the above purposes. figure 3.1 shows a sample system configuration using the ugm, and figure 3.2 shows an example of ugm mapping onto the cpu memory space. rev. 2.0, 09/02, page 34 of 366 cpu q2sd display data main memory ugm cpu bus figure 3.1 example of system configuration using ugm ugm cpu memory space 4 gbytes 0 frame buffer 0 frame buffer 1 background screen source patterns display list typical uses of ugm foreground screen figure 3.2 example of ugm mapping onto cpu memory space 3.2 q2sd access 3.2.1 ugm access priority the priority order for control of ugm access is as follows: 1. refreshing 2. display 3. video capture 4. cpu rev. 2.0, 09/02, page 35 of 366 5. others (command fetches, drawing, source referencing, etc.) to enable these different kinds of processing to be performed in parallel, after performing access for a fixed period, the q2sd passes the access control to another source. so if three sources are requesting access, for example, they will perform accesses alternately. 3.2.2 ugm access by the cpu the cpu can access the ugm as part of the memory space for the cpu. in a write operation, access is possible with a minimum number of wait cycles if there is empty space in the q2sds built-in 32-byte fifo buffer. in a read operation, a number of wait cycles are inserted. the number of wait cycles varies depending on the relationship between the q2sd operating clock and the display operating clock, and the screen size. the data stored in the fifo is transferred to the ugm when the rendering start bit in the system control register (the rs bit in sysr) is set to 1, when the ugm has not been accessed by the cpu for 32 tcyc0 or more, when the fifo is full, or when the ugm is accessed by the cpu. if a superh with mmu is used as the cpu, the ugm should be mapped onto a nor mal space as sram. data transfer between the cpu and q2sd is synchronized with the q2sds system operating clock. 3.2.3 ugm access by dmac data in the memory connected to the cpu bus can be transferred between the memory and the ugm using the dmac. dma transfer can be used to transfer display list or image data. single address mode or dual address mode can be used in dma transfers, since ugm memory addresses are controlled by the q2sds built-in address counter. the address mode is specifiable as single address mode or dual address mode. however, only cycle-steal mode can be used as the bus mode. note that the burst mode is not supported. see section 2.5.3, dma writes. 3.2.4 ugm access by q2sd sdram can be connected directly to the q2sd as the ugm. use of the sdram enables the q2sd to perform memory access in one-cycle (operating clock). sdrams that can be used for the ugm are those that have a power supply vo ltage of 3.3 v and meet the electrical characteristics and the initialization sequence of the q2sd. when the bus width of the sdram is 16 bits, up to two sdrams can be used. the following memory configurations can be used: rev. 2.0, 09/02, page 36 of 366 64-mbit capacity (1-mbit 16 4-bank configuration) 64-mbit capacity (512-kbit 32 4-bank configuration) 16-mbit capacity (512-kbit 16 2-bank configuration) the type of memory is set in the memory mode register (memr). 3.2.5 register access from the cpu the q2sd has address-mapped registers mapped onto the cpu byte address space (h'000 to h'7ff). these registers are divided into five groupsinterface control registers, memory control registers, display control registers (including the color palette registers), rendering control registers, and input data control registers. the color palette registers should be access in longwords. the address specification is made by inputting the address from pins a10 to a1 while the &6 pin is in the 0 state. a reserved addresses must not be read from or written to. reading or writing to these addresses may result in the loss of address-mapped register values, and unpredictable operation by the q2sd. to control ugm accesses, initial values must be set in the address-mapped registers by the cpu before it accesses the ugm. the setting procedure is shown in 1 to 3 below. 1. set initial values in the system control register ( sysr). set sres = 0, dres = 1, and den = 0. 2. set initial values in other registers. 3. set sres = 0 and dres = 0. also, since video control related registers (video area start address register 0 to 2 ( vsar0 to vsar2), video window size registers (vsizer), and video incorporation mode register (vimr)) are externally updated for video capture operations, they should only be rewritten when the vie bit is cleared to 0 in the video incorporation mode register. the same also applies when updating bits other than vie in vimr. the procedure is shown below. 1. clear the vie bit to 0 in vimr. retain bits other than vie to the values to which they are set at that time. 2. modify the contents of vsar0 to 2 and vsizer, and bits other than the vie bit in vimr after the elapse of one 996 cycle. 3. set the vie bit to 1 in vimr. retain bits other than vie to the values to which they are set at that time. rev. 2.0, 09/02, page 37 of 366 3.2.6 register updating external updating: in external updating, values set in address-mapped registers by the cpu become effective after the end of the cpu access. when the vbk flag and frm flag in the status register (sr) are set to 1 at the start of vertical blanking, display control related registers which are updated by the external updating, such as the color palette registers, are updated without causing display flicker. internal updating: in internal updating, values set in address-mapped registers become effective when q2sd internal updating is performed. in the case of registers with an internal update function, therefore, display flicker can be prevented even if the cpu modifies address- mapped registers relating to display operations without being aware of the display timing. internal updating is carried out while the dres bit is set to 1 in the system control register (sysr) and at the beginning of each frame. internal updating is also performed at the beginning of each field for wrap and bg bits in the display mode register ( dsmr), and bgsx and bgsy bits in inter lace sync & video mode. the update is performed at the falling edge of 96<1& when the tv sync mode setting in dsmr is tvm1 = 0, tvm0 = 0 (master mode), and on detection of the fall of (;96<1& when tvm1 = 1 and tvm0 = 0 (tv mode). internal updating is not performed when tvm1 = 0 and tvm0 = 1. the address-mapped registers provided with an internal update function are shown in table 3.1. the initial values of these registers should be set while the dres bit is set to 1. however, internal updating is used for display start address registers 0, display start address register 1, and the gbm bits in the rendering mode register in display operations. in drawing operations, external updating is used. internal updating is used for the video area start address (vsar 0 to 2), video area start coordinates (vpr), and video display size (vsize) in display operations. in video capture operations, external updating is used. rev. 2.0, 09/02, page 38 of 366 table 3.1 registers with internal update function q2 control registers address a[10:0] name abbreviation bits with internal update function h000 system control register sysr den (bit 13) h00a display mode register dsmr wrap (bit 11) bg (bit 10) h00c rendering mode register remr gbm (bits 2C0) h056 display mode 2 register dsmd2 all bits memory control registers address a[10:0] name abbreviation bits with internal update function h010 display size register x dsrx all bits h012 display size register y dsry all bits h014 display start address register 0 dsar0 all bits h016 display start address register 1 dsar1 all bits h04c background start coordinate register x bgsrx all bits h04e background start coordinate register y bgsry all bits display control registers address a[10:0] name abbreviation bits with internal update function h026 display window register (horizontal display start position) dswr (hds) all bits h028 display window register (horizontal display end position) dswr (hde) all bits h02a display window register (vertical display start position) dswr (vds) all bits h02c display window register (vertical display end position) dswr (vde) all bits h02e horizontal sync pulse width register hswr all bits h030 horizontal scan cycle register hcr all bits h032 vertical sync position register vspr all bits h034 vertical scan cycle register vcr rev. 2.0, 09/02, page 39 of 366 display control registers (cont) address a[10:0] name abbreviation bits with internal update function h03a color detection register h cderh all bits h03c color detection register l cderl all bits h058 video display position register (horizontal display start position) vpr (hvp) all bits h05a video display position register (vertical display end position) vpr (vvp) all bits h062 video area start address register 0h vsa0h all bits h064 video area start address register 0l vsa0l all bits h066 video area start address register 1h vsa1h all bits h068 video area start address register 1l vsa1l all bits h06a video area start address register 2h vsa2h all bits h06c video area start address register 2l vsa2l all bits h06e video window size register x vsizerx all bits h070 video window size register y vsizery all bits h074 cursor register (horizontal start position 1) csr (hcs1) all bits h076 cursor register (vertical start position 1) csr (vcs1) all bits h078 cursor register (horizontal start position 2) csr (hcs2) all bits h07a cursor register (vertical start position 2) csr (vcs2) all bits h07c cursor area start address register 1 csar1 all bits h07e cursor area start address register 2 csar2 all bits 3.2.7 byte exchange function the word data can be replaced between upper and lower data in byte units by using the dtp and mdtp of the input data transfer mode register (iemr). mdtp is referenced when the data is directly transmitted to the ugm, and dtp is referenced when the d ata is transmitted to the ugm via the image data entry register (ider). rev. 2.0, 09/02, page 40 of 366 main memory q2sd ugm 1 word 1 word h'aa h'bb h'aa h'bb h'cc h'dd h'ee h'ff h'bb h'aa h'bb h'aa h'dd h'cc h'ff h'ee .... .... .... .... figure 3.3 byte exchange diagram 3.2.8 2-dimensional image data exchange function conversion of 2-dimensional image data: image data which is stored in the linear address format in the main memory, etc., can be converted to the two-dimension image data and transferred to ugm. when the image data is transmitted to the image data entry register (ider) using the cpu, the q2sd converts the data to the two-dimension image data and stores it in ugm. the supported d ata format is shown below. for details of the data format, section 3.2.9, input color data configurations, and section 3.2.10, configurations of data in ugm. ider input data ugm data linear address d yuv data ( d y, d u, d v 4 bits each) ? two-dimension rgb data (r: 5 bits, g: 6 bits, b 5 bits) linear address (yuv data (4:2:2 format)) ? two-dimension rgb data (r: 5 bits, g: 6 bits, b 5 bits) linear address (16 bits/pixel data) ? two-dimension 16 bits/pixel data linear address (8 bits/pixel data) ? two-dimension 8 bits/pixel data the converted rgb data can be used for the source data of the 4-vertex screen drawing command and the data for each display screen. q2sd registers that should be set by the cpu are shown in figure 3.4. make the register settings in the order shown in figure 3.5. rev. 2.0, 09/02, page 41 of 366 (c) iemr: input data conversion mode q2sd internal registers (d) ider: image data entry (b) idsrx, y: image data size (a) isar: image data transfer start address main memory linear address image data memory width (512 or 1024 dots) is specified by the mwx bit in the rendering mode register (remr) x size (idsrx) y size (idsry) ugm source area two-dimension data start address (isar) figure 3.4 image data specifications (d) write to ider: image data entry (c) set iemr (bits yuv2, 1, 0): input data conversion mode the setting procedure is shown in the following table. values to be set in yuv2, yuv1, yuv0 yuv2 0 0 0 1 yuv1 0 1 1 1 yuv0 1 0 1 1 set (0, 0, 1) in (yuv2, 1, 0). set (0, 1, 0) in (yuv2, 1, 0). set (0, 0, 0) in (yuv2, 1, 0), then set (0, 1, 1) in (yuv2, 1, 0). set (1, 0, 0) in (yuv2, 1, 0), then set (1, 1, 1) in (yuv2, 1, 0). setting procedure set the following: (a) isar: image data transfer start address (b) idsrx, y: image data size figure 3.5 register setting procedure for d yuv/yuv-to-rgb conversion 2. sample settings for two-dimension image by dma transfer when performing two-dimension image conversion by dma transfer, ensure that the number of pixels corresponding to dma transfer word count registers h and l (dmawrh, dmawrl) is the s ame as the total number of pixels specified by image data size registers x and y (idsrx, idsry). rev. 2.0, 09/02, page 42 of 366 if these two values are not the same, dma transfer w ill end at the smaller of the two values, and then bits yuv2, yuv1, and yuv0 w ill be cleared to 000, and bits dma1 and dma0 will be cleared to 00 again. therefore, if the total transfer word count of the source data is larger than the dma transfer word count, dmawr, the dma s etting must be divided into a number of stages. the image data transfer start address register (isar) must be set each time this conversion is performed. 3. an example of the settings for transferring 320 240 yuv source d ata to ugm by means of four dma_yuv oper ations 320 320 60 60 60 60 yuv source rgb data 320 240 240 h'000000 q2sd figure 3.6 example of settings for transferring 320 240 yuv sou rce data to ugm by means of four dma operations conditions: ? yuv source s ize: 320 240 dots ? number of setting stages: 4 ? ugm transfer destin ation address: h'000000 ? yuv mode: yuv-rgb conversion 1st time (1) image data transfer start address setting isar = h'000000 (2) image data transfer size register settings *1 idsrx = 320 idsry = 60 (3) dma transfer word count s etting *2 dmawr = 19200 (4) yuv mode s etting iemr = h'01 (5) dma mode s etting dma in sysr = h'11 (6) wait until the dmf bit in the s tatus register (sr) changes to 1. 2nd time onward (7) image data transfer start address re-setting *3 isar = current isar + transfer word count (y) = h'c180 rev. 2.0, 09/02, page 43 of 366 (8) image data transfer size register settings *4 idsrx = 320 idsry = 60 (9) dma transfer word count s etting *5 dmawr = 19200 (10) yuv mode s etting iemr = h'01 (11) dma mode s etting dma in sysr = h'11 steps (6) to (11) are then repeated until the end of the yuv transfer source. s ettings for yuv-rgb conversion are also made as shown in the above example. notes: 1. where idsrx and idsry satisfy the following conditions: ? the transfer unit is a line. ? one transfer is within the dmawr range. 2. set the transfer word count corresponding to idsrx/idsry. 3. in the q2sd, addresses of the foreground screen area are allocated as shown in section 3.3.2, memory map. therefore, set the drawing data transfer start address in isar with reference to the relationship between memory physical addresses and coordinates shown in figure 3.9). in this setting example, the start position of the second image data transfer is at the [x = 0, y = 60] dot position. this position is divided into the upper and lower coordinates of x and y, respectively, and the value assigned in figure 3.9 is the value set in isar the second time. example: method of calculating second isar, with memory width of 512 (from figure 3.9) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 idsyr = 60 y = idsyr 512 value current isar calculation result = h'c180 y upper y lower rev. 2.0, 09/02, page 44 of 366 example: method of calculating second isar, with memory width of 1024 (from figure 3.9) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 1 2 3 4 5 6 7 y upper y lower 8 9 10 11 12 13 14 15 0 0 1 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 idsyr = 60 y = idsyr 1024 value current isar calculation result = h'18180 notes: 4. same setting conditions as for (2). 5. same setting conditions as for (3). 3.2.9 input color data configurations input data configurations are shown below. the pixel number starting with 0 runs from left to right in ascending order. 16-bit data 0 15 d15 to d0 pixel no. 1 word 8-bit data 0 15 1 d15 to d0 pixel no. 87 0 1 byte 1 byte 1 bit/pixel data 0 0 15 d15 to d0 pixel no. 14 15 14 1 word rev. 2.0, 09/02, page 45 of 366 8-bit/pixel data 0 15 1 d15 to d0 pixel no. 87 0 1 word rgb data (16-bit/pixel data) b (5 bits) g (6 bits) r (5 bits) 0 15 d15 to d0 11 10 5 4 1 word yuv data yuv d ata uses a 4:2:2 format. the u and v data is horizontally reduced data. 0 15 y0 d15 to d0 image data (1st word) 87 u0 0 15 y1 d15 to d0 image data (2nd word) 87 v0 0 15 y2 d15 to d0 image data (3rd word) 87 u2 0 15 y3 d15 to d0 image data (4th word) 87 v2 0 15 yn-1 d15 to d0 image data (nth word) 87 vn-2 1 word data flow n: even number rev. 2.0, 09/02, page 46 of 366 d yuv data d yuv d ata uses a raster as the basic unit. the data configuration for one raster consists of the initial value in the first two words and compressed image data in the remaining words. d y0 d u0 d y1 d v0 d yn-2 d un-2 d yn-1 d vn-2 d y2 d u2 d y3 d v2 0 15 0 d15 to d0 initial value (1st word) 87 y 1 word 0 15 d15 to d0 initial value (2nd word) 87 uv 1 word 0 15 d15 to d0 image data (3rd word) 87 43 12 11 43 12 11 43 12 11 1 word 0 15 d15 to d0 image data (4th word) 87 1 word 0 15 d15 to d0 image data (nth word) 87 1 word data flow rev. 2.0, 09/02, page 47 of 366 ycbcr data the data is input from the video capture input. the ycbcr data is eight bits in 4:2:2 format. 0 7 vin7 to vin0 image data (5th byte) cb2 0 7 vin7 to vin0 image data (6th byte) y2 0 7 vin7 to vin0 image data (7th byte) cr2 0 7 vin7 to vin0 image data (8th byte) vin7 to vin0 image data (nth byte) y3 0 data flow 7 yn 0 7 vin7 to vin0 image data (1st byte) cb0 0 7 vin7 to vin0 image data (2nd byte) y0 0 7 vin7 to vin0 image data (3rd byte) cr0 0 7 vin7 to vin0 image data (4th byte) y1 3.2.10 configurations of data in ugm the ugm d ata configuration is shown below (first for a ugm 16-bit bus, then for a 32-bit bus). the image data is handled as little endian format by the q2sd. the pixel number starting with 0 runs from left to right in ascending order. 16-bit data 0 15 md15 to md0 1 word 0 15 1 word 16 31 1 word address 4n + 2 address 4n md31 to md0 rev. 2.0, 09/02, page 48 of 366 1-bit/pixel data 0 0 15 md15 to md0 pixel no. 14 15 14 1 word 0 0 15 14 15 14 1 word 16 16 31 30 31 30 1 word md31 to md0 8-bit/pixel data 0 15 1 md15 to md0 pixel no. 87 0 1 word 16 31 3 24 23 2 1 word 0 15 1 87 0 1 word md31 to md0 pixel no. rgb data (16-bit/pixel data) b (5 bits) g (6 bits) r (5 bits) 0 15 md15 to md0 11 10 5 4 1 word b1 (5 bits) g1 (6 bits) r1 (5 bits) 16 31 27 26 21 20 1 word b0 (5 bits) g0 (6 bits) r0 (5 bits) 0 15 11 10 5 4 1 word md31 to md0 rev. 2.0, 09/02, page 49 of 366 ycbcr data ( yuv d ata) ycbcr (yuv) d ata uses a 4:2:2 format. cr and cb (u and v) data is horizontally reduced data. 0 15 y0 md15 to md0 image data (1st word) 87 cb0 (u0) 16 31 y1 24 23 cr0 (u0) 0 15 y0 87 cb0 (v0) 0 15 y1 md15 to md0 image data (2nd word) 87 cr0 (v0) 0 15 y2 md15 to md0 image data (3rd word) 87 cb2 (u2) 0 15 y3 md15 to md0 image data (4th word) md15 to md0 image data (nth word) image data (1st longword) 16 31 y3 24 23 cr2 (u2) 0 15 y2 87 cb2 (v2) image data (2nd longword) 16 31 y2n-1 24 23 cr2n-2 (u2n-2) 0 15 y2n-2 87 cb2n-2 (v2n-2) image data (nth longword) 87 cr2 (v2) 0 n: even number data flow 15 yn-1 87 cn-2 (vn-2) 1 word 1 word 1 word data flow md31 to md0 md31 to md0 md31 to md0 3.2.11 q2sd internal data format color data configurations in the q2sd are shown below. rgb data the display data configurations used in the display unit is shown below. ? when the ugm d ata is 16 bits/pixel and the color palette is not used a pixel with h0000 on the foreground or cursor screen is a transparent color and the data on the lower screens shows through regions set to this color. 0 12 11 6 5 dd17 to dd0 18 bits 17 msb lsb msb lsb msb lsb r (5 bits) 0 0 g (6 bits) b (5 bits) rev. 2.0, 09/02, page 50 of 366 ? when the ugm d ata is 8 bits/pixel and the color palette is used, or the ugm d ata is ycbcr format a pixel with h00000000 on the foreground or cursor screen is a transparent color and the data on the lower screens shows through regions set to this color. 0 12 11 6 5 dd17 to dd0 18 bits 17 r (6 bits) b (6 bits) g (6 bits) msb lsb msb lsb msb lsb dd17 to dd0 are internal signals. q2sd analog output is the result of d/a conversion of the above data. color palette register color data configuration ? the color palette register color data configuration is shown below. h0000 0000 is a transparent color and the data on the lower screens shows through regions set to this color. msb r (6 bits) 0 lsb 15 d15 to d0 register address even word 87 msb 21 b (6 bits) g (6 bits) 0 lsb 15 odd word 10987 msb lsb 21 1 word d15 to d0 3.2.12 interrupt output function the q2sd outputs interrupt output signal caused by various sources. the generation of interrupt source is reflected in the status register (sr). the selection of interrupt source is set in the interrupt enable register (ier) for use by transfer of the display list or source data to ugm, controlling cursor blinking, controlling dma transfer, and error processing, etc. rev. 2.0, 09/02, page 51 of 366 table 3.2 interrupt output function status register (sr) bit description processing tvr the expected signal ( (;96<1& ) is not input error processing frm the display frame is switched drawing processing, display processing, and data transfer processing dmf dma transfer is completed data transfer processing cer invalid command is detected error processing vbk the display field is switched drawing processing, display processing, and data transfer processing tra the trap command is executed drawing processing, display processing, and data transfer processing csf the frame is changed before the completion of the command error processing brk command execution is aborted by the rbrk bit of the system control register (sysr) drawing is aborted and restarted. debugging by software is performed. 3.3 unified graphics memory (ugm) 3.3.1 memory address (1) one memory unit the q2sd performs ugm address control. the ugm includes the display list area, binary source area, 8-bit/pixel or 16-bit/pixel source area, 8-bit/pixel or 16-bit/pixel rendering area, binary work area, and video area. the ugm is configured in 512-byte units, and a different memory configuration is used for each area. the memory configuration for each of the areas is shown in figure 3.7. the ugm consists of addresses that are consecutive within one memory unit (linear addresses), as shown in figure 3.8. rev. 2.0, 09/02, page 52 of 366 h'00 bit 0 h'00 bit 1 h'00 bit f h'01 bit 0 h'ff bit 0 h'ff bit 1 .... .... .... h'ff bit f 1 word 4096 bits 32 bytes 8 bits h'00 lower byte h'00 upper byte h'01 lower byte ...... ...... h'0f upper byte .... .... h'f0 lower byte h'f0 upper byte h'f1 lower byte ...... h'ff upper byte 16 lines 16 words 16 bits h'00 h'01 ...... ...... h'0f .... .... h'f0 h'f1 ...... h'ff 16 lines 16 bits/pixel (multi-valued source, multi-valued destination, video): 1-bit/pixel (work, binary source, display list): 8 bits/pixel (multi-valued source, multi-valued destination): figure 3.7 configuration of one memory unit (512 bytes) rev. 2.0, 09/02, page 53 of 366 16 lines 16 lines one memory unit (512 bytes) 512 or 1024 dots 32 bytes figure 3.8 ugm address transitions (2) 2-dimensinal virtual addresses the q2sd handles the ugm as a 2-d imensinal virtual address space. the 2-dimensinal virtual address space is represented by the x-axis corresponding to the horizontal direction of the display and the y-axis corresponding to the vertical direction. the original corresponds to a physical address of h 00 in the ugm. the possible range on the x-axis is from 0 to 511 or from 0 to 1023, and that on the y-axis is 0 or greater. the q2sd processes displaying and drawing based on the 2-dimensinal virtual addresses. conversion between 2-dimensinal virtual addresses and ugm phys ical addresses shown in figure 3.9 is performed by the q2sd. the upper bits of the x coordinate and lower bits of the x coordinate refer to the values when the x values are divided into the respective bit widths. similarly, the y upper coordinate and y lower coordinate are the values when the y values are divided. when the cpu directly accesses the ugm to modify the image data, take this conversion account into consideration. (3) linear addresses the q2sd can handle part of the ugm as a linear address sp ace. the area should be specified to the linear address space and the start address in the ugm should be sp ecified. the addresses of this area is represented by physical addresses. rev. 2.0, 09/02, page 54 of 366 upper bits of y coordinate upper bits of x coordinate lower bits of y coordinate lower bits of x coordinate a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 upper bits of y coordinate upper bits of x coordinate lower bits of y coordinate lower bits of x coordinate a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 upper bits of y coordinate upper bits of x coordinate lower bits of y coordinate lower bits of x coordinate a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 upper bits of y coordinate upper bits of x coordinate lower bits of y coordinate lower bits of x coordinate a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 upper line: ugm physical addresses (bytes) a22 to a1, a0 lower line: 2-dimensional virtual addresses (x, y) 8 bits/pixel, mwx = 0 (512 pixels) 8 bits/pixel, mwx = 1 (1024 pixels) 16 bits/pixel, mwx = 1 (1024 pixels) 16 bits/pixel, mwx = 0 (512 pixels) note: a0 is an lsi internal signal, indicating the least significant bit of the byte address. the least significant bit of the byte address is decoded and output to pins udqm0, udqm1, ldqm0 and ldqm1. figure 3.9 correspondence between ugm physical addresses (bytes) and 2-dimensinal virtual addresses (4) work addresses the q2sd handles part of the ugm as a work address sp ace. work addresses are 2-dimensinal addresses and one dot corresponds to one address. the work address space starts from the address specified by the work area start address register (wsar). the work address space configures a 2-dimensional space by wrapping around at every 512 or 1024 pixels. the number of pixels for wrap-around is specified by the memory width bit in the rendering mode register (the mwx bit in remr). figures 3.10 and 3.11 show the examples. rev. 2.0, 09/02, page 55 of 366 the memory capacity required for the work address space is (the number of pixels specified by the mwx bit) (ymax in the sclip co mmand + 1)/8 [bytes]. in general, one less than the number of display lines in the vertical direction should be set as ymax in the sclip co mmand. 0 511 work area display list and binary source work area start address: h'40000 display list start address: h'44000 512 544 conditions: 8 bits/pixel 512-pixel memory width (mwx = 0) figure 3.10 work address space ... .. .. . .. lsb msb h'40000 h'40001 ...... ...... 0 0 511 1 memory unit (512 bytes) = 1 line of work address space h'4003f h'40040 h'40041 ...... 1 h'4007f .. . .. .. . .. h'401c0 h'401c1 ...... 7 h'401ff h'43fc0 h'43fc1 ...... 255 h'43fff work address y work address x 8 dots 8 dots 8 dots 32 memory units = 32 lines of work address space ugm physical address work area start address h'40000 figure 3.11 relationship between ugm physical addresses (byte) and work addresses rev. 2.0, 09/02, page 56 of 366 (5) ugm physical addresses the ugm addresses range from h 000000 to h 37fffe when two memories of 16 mbits 16 or from h 000000 to h 7ffffe when a single memory of 64 mbits 32. 3.3.2 memory map figure 3.12 shows a memory map of the ugm. a combin ation of 8-bit/pixel and 16-bit/pixel areas can be used in the ugm, but area allocation must be carried out so that areas do not overlap. for this purpose, 8-bit/pixel and 16-bit/pixel areas should virtually be considered as shown in figure 3.13 when performing area allocation. in terms of the number of y-direction dots, there is a 2-to-1 relationship between the 8-bit/pixel and 16-bit/pixel memory maps. rev. 2.0, 09/02, page 57 of 366 (0, 0) 0 479 512 [dsa1] (x = 0, y = 256l) [wsah, wsal] (x = 0, y = 16n) [ssah, ssal] (x = 0, y = 16m) [dlsah, dlsal] [csah1, csal1] bgsy foreground screen (fg) (frame buffer fb0) y x foreground screen (fg) (frame buffer fb1) video area (v0) video area (v1) display list 1 display list 2 work area multi-valued source area background screen (bg) video area (v2) [vsah0, vsal0] [vsah1, vsal1] [vsah2, vsal2] [wsah, wsal] [ssah, ssal] (bgsx, bgsy) (639, 0) (1023, 0) bgsx 16 mbits 2 [dsa0] (x = 0, y = 256l) l, m, n: multiplier [csah2, csal2] ugm a b a b cursor 1 with blink function cursor 2 with blink function figure 3.12 sample memory map (corresponding to 640 480 screen size, with 16 bits/pixel ) rev. 2.0, 09/02, page 58 of 366 [wsah, wsal]: addresses which can be sp ecified by bits a22 to a13 [ssah, ssal]: addresses which can be sp ecified by bits a22 to a13 [dsa0], [dsa1]: addresses which can be specified by bits a22 to a16 [dlsah, dlsal]: addresses which can be sp ecified by bits a22 to a5 [vsahn, vsaln]: addresses which can be sp ecified by bits a22 to a10 (n = 0, 1, and 2) 0 fb0 fb1 0 0 512 512 (dots) 1024 (dots) 1023 0 16-bits/pixel memory map 8-bits/pixel memory map 1023 ugm ugm figure 3.13 relationship between 8-bits /pixel and 16-bits/pixel memory maps rev. 2.0, 09/02, page 59 of 366 if a 1024-pixel memory width configuration is used when the horizontal screen size is 512 pixels or less (e.g. 320 240 equivalent), the foreground screen fb1 can be set from position x = 512 by setting the hdis bit in display mode register 2 ( dsmr2) to 1. in this case, the same value is set in dsa0 and dsa1. when the hdis bit is set to 1, use the following s ettings: gbm2 = 0, bm1 = 0, and rsae = 0. ! " # ! " # 0 1023 fb0 fb1 mwx = 1 hdis = 0 0 1023 fb0 fb1 mwx = 1 hdis = 1 512 figure 3.14 example of frame buffer fb1 location when hdis = 1 3.3.3 coordinate systems (1) coordinates the q2sd has screen coordinates for display control, rendering, work, multi-valued source, and binary source coordinates for drawing control, and foreground screen, background screen, video screen, and cursor coordinates for display screen. in the q2sd 2-dimensional coordinates, a set of coordinates indicates a single pixel (except for video coordinates in ycbcr format). an x coordinate corresponds to the horizontal direction of the display screen and a y coordinate corresponds to the vertical direction. the positive coordinates indicate the right direction for x coordinates and the lower direction for y coordinates. there are three types of the correspondences between coordinates and ugm addresses: 2- dimensional virtual addresses, linear addresses, and work addresses. the coordinates in which addresses can be handled as 2-dimensional virtual addresses are screen, rendering, multi-valued source, foreground screen, background screen, and video screen coordinates. however, the multi-valued source coordinates are handled as 2-dimensional virtual addresses only when lni = rev. 2.0, 09/02, page 60 of 366 0 (source linear specification of the rendering attribute). the coordinates in which addresses can be handled as linear addresses are multi-valued source, binary source, and cursor coordinates. the coordinates in which addresses can be handled as work addresses are work coordinates. for details of the 2-dimensional virtual, linear, and work addresses, see section 3.3.1, memory address. (2) screen coordinates the screen coordinates are for display control. the origin of this coordinates corresponds to the upper-left of the display area. a step of the x coordinates corresponds to a dot and a step of the y coordinates corresponds to a line (one raster). for example, the upper-left and lower-right coordinates of the yw-by-xw display area are (0, 0) and (xw - 1, yw - 1) in the screen coordinates. the correspondences vary in each display screen. the origin of the foreground screen corresponds to that of the screen coordinates. the start coordinates of the background screen are the same as that of the screen coordinates. the origins of the video and cursor screens are within the screen coordinates specified by the video display start position registers (vpr) and cursor display start position registers (csr). the maximum x values in the screen coordinate is 1023 or 511 which is specified by the memory width bit in the rendering mode register (the mwx bit in remr). video screen origin (hvp - 1, vvp - 1) background screen start coordinates min. setting 511 max. setting 1023 x (0, 0) y screen coordinates foreground screen origin cursor 1 screen origin (hcs1 - 1, vcs1 - 1) (xw - 1, yw - 1) cursor 2 screen origin (hcs2 - 1, vcs2 - 1) figure 3.15 screen coordinates rev. 2.0, 09/02, page 61 of 366 (3) rendering coordinate system this is the coordinate system used for drawing control as destination coordinates for drawing commands. it has a fixed size as shown in figure 3.15. the coordinates which exceeds the fixed size cannot be handled. the origin of the rendering coordinates corresponds to the display address register (dsar0 and dsar1) contents when the rsae bit in the rendering mode register (remr) is cleared to 0, and the rendering start address register (rsar) contents when the rsae bit in the rendering mode register (remr) is set to 1. eight bits or 16 bits of data width (8 bits/pixel or 16 bits/pixel) for a set of the rendering coordinates can be selected by the graphic bit mode bits in the rendering mode register (bits gbm 2 to gbm 0 in remr). drawing operations for coordinates outside the clipping area are performed. however, accesses to the ugm are not performed. the rendering coordin ates origin can be shifted in both horizontal and vertical directions by the offset specified by the local offset command (lc ofs). in this case, the coordinates to which the offset values xo and yo specified by the lcofs command are added must be within the range shown in the following expressions. of all drawing commands, the commands which specifies clipping (sclip and uclip) are handled as the rendering coordinates without offset. (when bold line attribute is specified) C2045 x + xo 2044 C2045 y + yo 2044 (when bold line attribute is not specified) C2048 x + xo 2047 C2048 y + yo 2047 rev. 2.0, 09/02, page 62 of 366 rendering coordinates rendering coordinates when offset values = (a, b) y offset C2048 C2048 x rendering coordinate origin (without offset) (0, 0) (a, b) rendering coordinate origin (with offset) when offset values = 0 the size of the logical space from the rendering coordinate origin in accordance with the offset values never exceeds 2047. y C2048 2047Ca x 2047 offset C2048+b 2047 x (0, 0) rendering coordinate origin (without offset) (Ca, Cb) when offset values = (Ca, Cb) the size of the logical space from the rendering coordinate origin in accordance with the offset values never exceeds 2047. y 2047 C2048+a rendering coordinate origin (0, 0) 2047Cb 2047 C2048 rendering coordinates rendering coordinate origin (with offset) figure 3.16 rendering coordinates rev. 2.0, 09/02, page 63 of 366 (4) multi-valued source coordinates this is the coordinate system used for drawing control and handles multi-valued source data (graphics bit map data and natural images) specified by drawing commands. data width of 8 bits or 16 bits for a set of the multi-valued source data coordinates (8 bits/pixel or 16 bits/pixel) can be selected by the graphic bit mode bits in the rendering mode register (bits gbm 2 to gbm 0 in remr). data width of the multi-valued source coordinates is determined by the bit configuration specified by this register setting. the q2sd can use two kinds of multi-valued source coordinates according to the value of linear attribute lni. when lni = 0, the coordinate origin is specified by the multi-valued source area start address. figure 3.17 shows the multi-valued source coordinates when lni = 0. as shown in this figure, the maximum coordinate system size is represented by 1024 1024 positive coordinates, but the size depends on the installed memory capacity, screen size, and multi-valued source area start address. depending on the multi-valued source start address, this coordinate system may entirely or partially overlap another coordinate system. when data is transferred from the cpu, address conversion shown in figure 3.9 is needed. if the function of 2-dimensional image data conversion is used (see section 3.2.8, 2-dimensional image data exchange function), the address conversion shown in figure 3.9 is performed by the q2sd. when lni = 1, it is possible to use multi-valued source arranged in linear fashion in the ugm. the physical address of the origin and the range of the coordinates are specified by the parameters in a drawing command. each multi-valued source data indicates one physical address (origin: upper-left of the multi-valued source data coordinates) and specify the area (length and width) by the source address parameters (tdx and tdy) in the pol ygon4a co mmand. this area can overlap another coordinate system such as a display list. figure 3.18 shows the multi- valued source coordinates when lni = 1. rev. 2.0, 09/02, page 64 of 366 (max) 1023 (max) 1023 (0, 0) y x ssar figure 3.17 multi-valued source coordinates (lni = 0) tdx tdy source address (byte) polygon4a command parameters source address tdx tdy (0, 0) figure 3.18 multi-valued source coordinates with lni = 1 specified (linear address) (5) binary source coordinates this is the coordinate system used for drawing control and handles binary source data (character and line patterns) specified by drawing commands. data width of a single bit for a set of the binary source data coordinates (1 bit/pixel) is used. the physical address of the origin and the range are specified by the parameters in a drawing command. each binary source data indicates one physical address (origin: upper-left of the binary source data coordinates) and specify the area (length and width) by the source address parameters (tdx and tdy) in the pol ygon4b co mmand. this area can overlap another coordinate system such as a display list. however, the start address of the source pattern must be a byte address. rev. 2.0, 09/02, page 65 of 366 tdx tdy source address (byte) polygon4b command parameters source address tdx tdy (0, 0) figure 3.19 binary source coordinates (6) work coordinate system this coordinate system is for drawing control and corresponds on a one-to-one basis to the rendering coordinate system, as shown in figure 3.20. when the work specification in the rendering attributes is set, a pattern is controlled using this coordinates. drawing commands for work data use this coordinates for drawing. data width of a single bit for a set of the work coordinates is used. the physical address of the origin, clipping, and offset are controlled the same way as the rendering coordinates. the physical address of the origin is specified by the work area start address register (wsar) rev. 2.0, 09/02, page 66 of 366 work coordinates work coordinates when offset values = 0 : physical coordinate space (memory-installed space) : display space for 320 240 screen configuration (system clipping space) offset 2047?b ?2048 x work coordinate origin (without offset) (0, 0) (a, b) work coordinate origin (with offset) when offset values = (a, b) the size of the logical space from the work coordinate origin in accordance with the offset values never exceeds 2047. y ?2048 2047?a offset ?2048+b 2047 x (?a, ?b) when offset values = (?a, ?b) the size of the logical space from the work coordinate origin in accordance with the offset values never exceeds 2047. y 2047 ?2048+a work coordinates work coordinate origin (with offset) (0, 0) work coordinate origin (without offset) 2047 ?2048 y ?2048 2047 work coordinate origin (0, 0) figure 3.20 work coordinates rev. 2.0, 09/02, page 67 of 366 (7) foreground s creen coordinate system this coordinate system is for display control and the foreground screen (fg(fb0 and fb1)) is handled by this coordinate system. the physical address of the origin is specified by the display start address register (dsar0 and dsar1). the display buffer uses the double buffer configuration by which the origin of this coordinates specified by dsar0 or by dsar1 as a display start address can be switched. data width of 8 bits or 16 bits for a set of this coordinates (8 bits/pixel or 16 bits/pixel) can be selected and a maximum value of the x coordinate of 511 or 1023 can also be selected. these settings are specified by the graphic bit mode and memory width bits in the rendering mode register (bits gbm 2 to gbm 0 and the mwx bit in remr). (8) background s creen coordinate system this coordinate system is for display control and the background screen (bg) is handled by this coordinate system. the physical address of the origin is fixed at h 0. display starts from the coordinate specified by the background start coordinate registers (bgsr). data width of 8 bits or 16 bits for a set of this coordinates (8 bits/pixel or 16 bits/pixel) can be selected and a maximum value of the x coordinate of 511 or 1023 can also be selected. these settings are specified by the graphic bit mode and memory width bits in the rendering mode register (bits gbm 2 to gbm 0 and the mwx bit in remr). (9) video screen coordinate system this coordinate system is for display control and the video screen is handled by this coordinate system. the physical address of the origin is specified by the video area start address registers (vsr0 to vsr2). the buffer for video capture and display uses the triple buffer configuration by which the origin of this coordinates specified by vsr0, vsr1, or vsr2 as a display (video capture) start address can be switched. data width of ycbcr and rgb format are 8 bits or 16 bits for a set of this coordinates (8 bits/pixel or 16 bits/pixel), respectively. this is specified by the rgb bit in the video incorporation mode register (vimr). the area of this coordinates is specified by the video window size registers (vsizer). (10) cursor coordinate system this coordinate system is for display control and the cursor is handled by this coordinate system. the physical address of the origin is specified by the cursor area start address registers (csar1 and csar2). display for cursor 1 starts from the origin specified by csar1 and display for cursor 2 starts from the origin specified by csar2. data width for a set of this coordinates is 8 bits (8 bits/pixel). both the x and y coordinates range from 0 to 31. rev. 2.0, 09/02, page 68 of 366 3.3.4 double-buffering control the q2sd uses double-buffering control to alternately switch the display and drawing areas located in the ugm. an area sw itching operation is called a display change. there are three types of mode for double-buffering control: auto display change mode, auto rendering mode, and manual display change mode. these are specified by the double-buffering mode bits (dbm) in the system control register. the start of drawing is specified by the rs bit. when double-buffering control is performed, frame changes are performed in frame units when the q2sd is operating in non-interlace or interlace mode, and in field units when operating in interlace sync & video mode. when the q2sd is operated in interlace mode, the frame flag (frm) in the status register is used for 96<1& synchronization pulse detection by the cpu. when the q2sd is operated in non- interlace mode, synchronization pulses are detected using the vertical blanking flag (vbk). when the q2sd is operating in interlace sync & video mode, since the first field corresponds to the even field and the second field to the odd field, synchronization pulses are detected using vbk or frm. the same results can also be achieved by using the vbkem command. double-buffer switching timing: ? non-interlace mode scanning system in which one frame is composed of one field. double-buffer switching is performed in units of a frame. ? interlace mode scanning system in which one frame is composed of two fields. double-buffer switching is performed in units of a frame. ? interlace sync & video mode scanning system in which one frame is composed of two fields. double-buffer switching is performed in units of a field. examples are given below for q2sd non-interlace operation, with a description of the operation in each mode. (1) auto display change mode in auto display change mode, display changes have priority. display is changed on completion of the frame. when drawing is completed within a frame periods, this mode can be used. if drawing is in progress when the frame is changed, drawing is aborted midway through that display list. it is therefore essential for drawing to be finished before the arrival of a 96<1& synchronization pulse. rev. 2.0, 09/02, page 69 of 366 an outline of operation in this mode is shown in figure 3.21. drawing cannot be started with the vbkem command in this mode, so the vbk or frm flag must be used. drawing is started by the rendering start bit (rs). interrupt handling fb0 display list transfer fb0: frame buffer 0 fb1: frame buffer 1 vbk flag: vertical blanking flag (bit 11 of status register (sr)) note: drawing is started by setting the rs bit to 1. fb1 display list transfer display screen: fb0 display screen: fb1 1st frame frame change frame change 2nd frame drawing destination: fb1 drawing to f1 aborted drawing destination: fb0 vsync (non-interlace operation) q2sd operation cpu operation interrupt handling interrupt by vbk flag interrupt by vbk flag * drawing start * drawing start figure 3.21 operation in auto display change mode (2) auto rendering mode i n auto rendering mode, display switching is not performed until execution of a trap command is completed. if drawing does not end within one frame, it is continued without interruption and display is changed in the frame on completion of drawing. an outline of operation in this mode is shown in figure 3.22. drawing is started by the rendering start bit (rs). rev. 2.0, 09/02, page 70 of 366 interrupt handling fb0 display list transfer fb0: frame buffer 0 fb1: frame buffer 1 vbk flag: vertical blanking flag (bit 11 of status register (sr)) note: drawing is started by setting the rs bit to 1. * drawing start interrupt by vbk flag interrupt is generated by vbk flag but is ignored as command has not finished. display switching is performed automatically at frame boundary immediately after end of drawing. fb1 display list transfer interrupt by tra flag display screen: fb0 1st frame 2nd frame 3rd frame drawing destination: fb1 * drawing start interrupt by vbk flag display screen: fb1 drawing destination: fb0 vsync (non-interlace operation) q2sd operation cpu operation interrupt handling interrupt handling figure 3.22 operation in auto rendering mode rev. 2.0, 09/02, page 71 of 366 (3) manual display change mode in manual display change mode, display changes and the start of drawing are controlled independently by software. frame changes can be performed by software by switching between fb0 and fb1 according to the setting of the dc bit in sysr, or by using the wpr co mmand to set the fb0 or fb1 start address in the display start address register indicated by dbf in the status register. the start of drawing is controlled by the rs bit in the system control register. interrupts by means of the vbkem command or the tra flag are used for the control timing. an outline of operation in this mode when using the dc bit is shown in figure 3.23. when changing from this mode to another double-buffering control mode, first check that the dc bit has been set to 1 and has then returned to 0. if this is not done, a display change will occur at a timing of vsync during display processing. confirm that the dc bit is cleared to 0 before setting it to 1. (4) control by means of vbkem and wpr commands the vbkem command holds fetching and execution of the display list waiting following this command. with the vbkem command , the waiting state is cleared at the next vsync in non- interlace mode display or interlace sync & video mode display, and at the start of the next frame in interlace sync mode display. use of this command allows drawing processing to be started without using a vbk or frm interrupt. control is carried out by a combination of the wpr command, which performs drawing-related register setting, and the vbkem command, which ends in synchronization with vbk, as shown in figure 3.24. the cpu only has to monitor drawing end interrupts; monitoring of vbk interrupts is no longer necessary. this kind of double-buffering control can be used only in auto-rendering mode and manual display change mode. rev. 2.0, 09/02, page 72 of 366 interrupt handling fb0 display list transfer interrupt by vbk flag interrupt is generated by vbk flag but is ignored as command has not finished. display area change (dc) bit is set, and screen is switched at next frame boundary. fb1 display list transfer interrupt by tra flag display screen: fb0 1st frame 2nd frame 3rd frame drawing destination: fb1 interrupt by vbk flag display screen: fb1 drawing destination: fb0 vsync (non-interlace operation) q2sd operation cpu operation interrupt handling interrupt handling fb0: frame buffer 0 fb1: frame buffer 1 vbk flag: vertical blanking flag (bit 11 of status register (sr)) tra flag: trap flag (bit 10 of status register (sr)) note: drawing is started by setting the rs bit to 1. * drawing start * drawing start figure 3.23 operation in manual display change mode rev. 2.0, 09/02, page 73 of 366 interrupt handling fb0 display list transfer fb1 display list transfer interrupt handling interrupt by tra display screen: fb1 display screen: fb0 0th frame 1st frame 2nd frame drawing destination: fb1 display address etc. set by wpr, synchronization performed by vbkem. display screen: fb1 drawing destination: fb0 vsync (non-interlace operation) q2sd operation cpu operation wpr vbkem wpr vbkem f1 display list activated. in manual change mode, display area change (dc) bit is set first. drawing start drawing start fb0: frame buffer 0 fb1: frame buffer 1 vbk flag: vertical blanking flag (bit 11 of status register (sr)) tra flag: trap flag (bit 10 of status register (sr)) note: drawing is started by setting the rs bit to 1. figure 3.24 operation when using vbkem command rev. 2.0, 09/02, page 74 of 366 3.3.5 refresh control the number of refresh cycles for the ugm conn ected to the q2sd is set in bits ref3 to ref0 (refresh cycle count) in the display mode register ( dsmr). the setting made in bits ref3 to ref0 is the number of refreshes per line (raster). for example, if the refreshing specification of the memory used is 4096 cycles/64 ms and one field is 1/60 sec, the necessary number of refresh cycles in one field is 1067 cycles. since the value set in dsmr is the number of refresh cy cles per lines (rasters), it is the quotient when 1067 is divided by the number of lines (rasters) in one field. the number of refresh cycles should therefore be set so that the following expression is satisfied: 1067 number of lines (rasters) number of refresh cycles set in dsmr the q2sd supports cas-before-ras refresh mode. the number of refreshes set in bits ref3 to ref0 are executed from the fall of the disp signal. table 3.4 shows sample settings. table 3.3 setting for number of refreshes bit 3: ref3 bit 2: ref2 bit 1: ref1 bit 0: ref0 operation 0 0 0 0 refresh timing is not output. **** refresh timing is set to any value from 1 to 15 cycles, and output. table 3.4 sample estimations of number of refresh cycles display screen size frame rate number of lines number of refreshes required per line ref set value 320 240 1/60 s 525/2 lines (1/60) (2/525) (4096/0.064) = 4.06 5 480 240 1/60 s 525/2 lines (1/60) (2/525) (4096/0.064) = 4.06 5 640 480 1/60 s 525 lines (1/60) (1/525) (4096/0.064) = 2.03 3 rev. 2.0, 09/02, page 75 of 366 3.4 display 3.4.1 display functions the q2sd has functions for outputting image data, drawn in the ugm, in synchron ization with externally or internally generated display timing. in the q2sd, horizontal and vertical display timing for the display screen is set in the display control registers (see section 5.4, display control registers). the display control register settings depend on the scanning and synchronization systems used. table 3.5 shows the display control register settings. figure 3.25 shows the display timing in non-interlace mode. the display screen is defined by the variables shown in table 3.6. set each of vdc, vde, vsp, and vc to the number of rasters within one 96<1& cycle for, regardless of the scan mode in the display mode register. set dsy to the number of rasters within one 96<1& cycle (one field) in non-interlace or interlace mode, or set dsy to two 96<1& cycles (one frame) in interlace sync & video mode. for the display operating clock (display dot clock) frequency, use the value obtained by dividing the number of pixels to be displayed in the xw period by the duration of the xw period. input the dot clock to the clk1 pin. display area hsw hc xw xs vc yw vsw ys figure 3.25 display timing rev. 2.0, 09/02, page 76 of 366 table 3.5 variables defined by display screen variable description unit hc horizontal scan cycle dot clock hsw horizontal sync pulse width dot clock xs interval between +6<1& rise and display screen horizontal display start position dot clock xw display screen display width per raster dot clock vc vertical scan cycle raster lines vsw vertical sync pulse width raster lines ys interval between 96<1& rise and display screen vertical display start position raster lines yw display screen vertical display interval raster lines rev. 2.0, 09/02, page 77 of 366 table 3.6 register settings operating mode register address (a10 - a0) register name bit name master mode tv sync mode 010 display size register x (dsrx) dsx * 5 xw xw 012 display size register y (dsry) dsy yw (2yw) * 6 yw (2yw) * 6 026 display window horizontal display start position register (dswr) hds * 2 * 3 hsw + xs - 11 hsw + xs - 14 028 horizontal display end position register (dswr) hde * 2 hsw + xs - 11 + xw hsw + xs - 14 + xw 02a vertical display start position register (dswr) vds * 1 * 4 ys - 2 ys - 2 02c vertical display end position register (dswr) vde * 1 ys - 2 + yw ys - 2 + yw 02e horizontal sync pulse width register (hswr) hsw hsw - 1hsw - 1 030 horizontal scan cycle register (hcr) hc hc - 1hc 032 vertical sync position register (vspr) vsp * 1 vc - vsw - 1 vc - vsw - 1 034 vertical scan cycle register (vcr) vc * 1 vc - 1 vc + 2 notes: 1. in all scanning mode the settings of the vds, vde, vsp, and vc bits are made for a one-field unit. 2. timing for the hds and hde are stipulated from the fourth rising edge of clk1 after the low level of (;+6<1& is detected at the rising edge of clk1. clk1 3. the setting for the lower limit of the hds bits is as follows: when mclk = 2 clk1, hds 3 64 (clk1/mclk); when mclk > 2 clk1, hds 3 (64 + 80) (clk1/mclk). the unit for mclk and clk1 is mhz. when mclk = 2 clk1, use a clock with which mclk and clk1 are synchronized. with a multiplication factor of n, mclk is n clk0. 4. in interlace and interlace sync & video mode, the setting is: vds 3 1. 5. use a value of 4 or more for dsx. if the cursor 1 horizontal display start position (hcs1) and cursor 2 horizontal display start position (hcs2) in the cursor registers are dsx, dsx - 1, dsx - 2, dsx - 3, dsx - 4, dsx - 5, then set dsx = xw + 6. 6. in interlace sync & video mode rev. 2.0, 09/02, page 78 of 366 3.4.2 screen display composition in the q2sd, the den (display enable) bit in the system control register ( sysr) can be used to select whether or not display data is to be output to the screen. when display data is not output, the display off output register (door) s ettings are displayed. the q2sd is capable of composing a screen from two cursor screens, a foreground screen (fg), a video screen, and a background screen (bg), and of displaying the screen thus composed. see figure 3.26. the data on the lower screens shows through regions of black (h 0) in the cursor and fg screens, since black is the transparent color for these screens. therefore, characters and pictures drawn on these screens using color other than black are composed with the image on the video screen. cursor screen foreground screen (fg) video screen background screen (bg) figure 3.26 configuration of the display screen for q2sd (1) composed screen types foreground screen: fg (frame buffer fb0 or fb1) video screen: vw background screen: bg cursors (cursor1 and cursor2) the foreground screens, video screens, and background screens that can actually be composed depend on the ugm bus width, the q2sd oper ating frequency, and the display operating clock frequency. see appendix e. (2) priority order of composed screens screens are displayed in the priority order shown below. with the cursors, display can be performed according to the priority order set in the window priority bits (pri) in display mode register 2 (dsmr2). foreground screen > video screen > background screen (in front-to-rear order) rev. 2.0, 09/02, page 79 of 366 (3) features of each screen foreground screen (fg) if the data for a foreground screen pixel is h 0 (color-expanded data by the color palette when 8 bits/pixel is selected), a low-priority screen such as the video window is displayed through that pixel. video screen (vw) in the video screen, the data in the ugm which is sp ecified by the contents of the video area start address registers (vsah and vsal) is displayed on a r ectangular area specified by the contents of the video window size registers (vsize). the video screen is not transparent to a low-display-priority screen such as the background screen and is displayed as a rectangular area. this window displays the video area specified by the video area start address registers (vsah and vsal) pointed to by the video window s tatus bit (vid) regardless of whether the video incorporation enable bit in the video incorporation mode register (the vie bit in vimr) is set to 1 or cleared to 0. background screen (bg) the display start position can be set in background coordinate display start registers x and y (bgsx, bgsy) in pixel units from address h 0 in the ugm. the background screen is suitable for performing scroll display. setting the wrap around bit in the display mode register (the wrap bit in dsmr) to 1 enables to access the display area in wrapping around way. when displaying the background screen, ensure that the frame screen and background screen locations in the ugm do not overlap. cursors two 32 32-pixel cursors with a hardware blink function can be displayed. if the cursor pixel data color-expanded by the color palette is h 0, a low-priority screen is displayed through that pixel. the blink cycle is specified by the cursor blink shape a display interval length or cursor blink shape b display interval length in the cursor display start position registers (the blinka or blinkb bit in csr). (4) display on/off control the bits that control whether or not each screen is displayed are shown below. with the foreground and background screens, set either or both to be displayed. when the foreground screen is set to 16-bit/pixel mode with bits gbm2 to gbm0, the q2sds internal display data increases and other screens cannot be displayed. therefore, to disable display of the video window, background screen, and cursors, the bits controlling whether or not each screen is to be displayed should be cleared to 0. in this case, also, clear the vie bit to 0 in the video incorporation mode register (vimr) to disable video capture. register updating for each screen should be carried out in the register update interval shown in section 3.2.6, register updating. the display contents differ according to the setting of the background screen wraparound mode (wrap) bit. rev. 2.0, 09/02, page 80 of 366 foreground screen: can be set with the fbd bit in display mode register 2 (dsmr2). video screen: can be set with the vwe bit in display mode register 2 (dsmr2). background screen: can be set with the bg bit in the display mode register (dsmr). cursors: can be set with bits ce1 and ce2 in display mode register 2 (dsmr2). table 3.7 background s creen related register settings register field name bit no. name set value notes dsmr 10 bg 1/0 combination on/off 11 wrap 1/0 wraparound on/off remr 2 to 0 gbm 000 to 111 8 or 16 bits/pixel bgsrx 9 to 0 bgsx bg starting point x coordinate according to screen coordinates bgsry 13 to 0 bgsy bg starting point y coordinate fb0 display screen bgsx bgsy 512 or 1024 16 mbits 1, 8 bits/pixel bg bgsx bgsy + scrolling achieved by changing start address specifies background screen start coordinates figure 3.27 example of background s creen simple scroll (wrap = 0) rev. 2.0, 09/02, page 81 of 366 fb0 4 display screen bgsx bgsy 512 or 1024 bgsy [13:09] + 2 3 2' 4' 3' 1 12 34 512 pixels (fixed) performs background screen wraparound. the wraparound unit is a rectangle comprising the memory width specified by the mwx bit in the x direction, and 512 pixels in the y direction. the start address is given by 0 in the x direction and bits [13:09] of bgsy in the y direction. 16 mbits 1, 8 bits/pixel figure 3.28 example of background s creen wraparo und scroll (wrap = 1) 3.4.3 scanning systems (1) q2sd scanning systems the q2sd allows selection of non-interlace mode, interlace mode, or interlace sync & video mode as the scanning system. the mode setting is made in the scm (scan mode) bits in the display mode register (dsmr). in non-interlace mode, one frame is composed of one field. in interlace mode, one frame is composed of two fields, even and odd, in which the same data is displayed. in interlace sync & video mode, also, one frame is composed of two fields, even and odd, but in this mode different data is displayed in these two fields. when the odev bit is cleared to 0 in display mode register 2 (dsmr2), the 2'') pin signal functions as follows. the order of fields to be displayed in interlace and interlace sync & video mode is specified by the odev bit in the display mode 2 register (dsmr2). when the odev bit is cleared to 0, an odd field and an even field for the same frame are displayed in that order. when the odev bit is set to 1, an even field and an odd field for the same frame are displayed in that order. in master mode, the q2sd outputs a high-level signal from the 2'') pin during even field display, and a low-level signal during odd field display. in tv sync mode, a high-level signal is input at the 2'') pin to display the even field, and a low-level signal to display the odd field. rev. 2.0, 09/02, page 82 of 366 when the odev bit is set to 1 in dsmr2, the polarity of the 2'') pin is the opposite of that described above. figure 3.29 shows examples of raster scan control display. vertical scan synchronization example non-interlace mode: 1/60 second/field, 1/30 second/field interlace mode: 1/30 second/frame interlace sync & video mode: 1/30 second/frame 00 01 02 03 04 05 06 07 08 09 non-interlace mode 00 01 02 03 04 05 06 07 08 09 interlace mode 00 01 02 03 04 05 06 07 08 09 00 02 04 06 08 0a 0c 0e 10 12 interlace sync & video mode 01 03 05 07 09 0b 0d 0f 11 13 raster scanned in odd field raster scanned in even field figure 3.29 examples of raster scan control display rev. 2.0, 09/02, page 83 of 366 (2) relationship with monitor display method the methods for display monitor devices are largely divided into two types. interlace sync method in this method, the input image data for an odd and an even lines is switched at every scanning cycle vc. one image (a single frame) is thus composed for 2 vc (the first 1-vc data is persistence of vision). this method is common for tvs and vcrs. rev. 2.0, 09/02, page 84 of 366 0 1 2 3 238 239 0 1 2 3 238 239 0 1 2 3 238 239 0 1 2 3 238 239 when the first field is an odd field and the second field is an even field, clear the odev bit to 0. (the odd and even fields belong to the same frame.) 1 3 5 7 477 479 0 2 4 6 476 478 0 2 4 6 476 478 1 3 5 7 477 479 display output (interlace) when the first field is an even field and the second field is an odd field, set the odev bit to 1. (the odd and even fields belong to the same frame.) even field odd field odd field even field even field odd field odd field even field when the first field is an odd field and the second field is an even field, clear the odev bit to 0. (the odd and even fields belong to the same frame.) display output (interlace sync & video) when the first field is an even field and the second field is an odd field, clear the odev bit to 0. (the odd and even fields belong to the same frame.) figure 3.30 display by interlace sync method non-interlace method in this method, the input image data is displayed at a time without any intervals. some high- resolution monitors use this method. rev. 2.0, 09/02, page 85 of 366 0 1 2 3 4 5 6 7 478 476 477 479 display output (interlace) the odev bit and the signal are not used. figure 3.31 display by non-interlace method some display devices receive data in the interlace sync method and display the data in the non-interlace method (progressive conversion function). in this case, the first-half data stored in memory in the display device and the second half data are displayed at one time. since the display is changed one time for 2 vc, clearness is increased, however, resolution is the same. since a multi-scan monitor has a function for selecting the vertical scanning frequency of 55 to 160 hz and the horizontal scanning frequency of 31 to 96 hz, improvement of resolution can be achieved. select an appropriate method of the q2sd output to match the input method of the monitor used. table 3.8 shows the possible combinations. table 3.8 combinations of q2sd output and monitor input methods monitor input method q2sd non-interlace mode q2sd interlace sync mode q2sd interlace sync & video mode interlace sync blurring blurring available non-interlace available available display size halved. blurring (1) non-interlace mode display the non-interlace mode is selected by setting the scan-mode bits in the display mode register (bits scm1 and scm0 in dsmr) to b 00. in a non-interlace display, the display on the screen is updated at 59.94 frames/sec. this mode allows the display of high-quality images, since the speed of switching is high. the non-interlace mode is used to output images for non-interlace monitors. rev. 2.0, 09/02, page 86 of 366 the data read from the ugm as d ata for display includes the fg, bg, vw, cursor 1, and cursor 2, according to the settings in dsmr and dsmr2. the value of vid for the vw screen is checked on each field. bg v1 fb1 ugm fb0 vsync q2sd images (fb0, bg, and v0) are output. vid checked. vid checked. q2sd images (fb1, bg, and v1) are output. v0 v2 figure 3.32 non-interlace mode display output rev. 2.0, 09/02, page 87 of 366 (4) interlace mode interlace mode is entered by setting the scan-mode bits in the display mode register (bits scm1 and scm0 in dsmr) to b 10. in interlace display driven by the q2sd, the data output in each pair of an even and odd field is for the same frame. the display is at 29.97 frames/sec. and the screen switching speed is reduced. since interlace mode is used to output to the interlaced display, the data read from the ugm includes the data for display as fg, bg, vw, cursor 1, and cursor 2, according to the settings in dsmr and dsmr2. vid of the vw screen is checked for each frame. vsync bg v1 fb1 ugm fb0 v0 v2 fb0, bg, and v0 are output. vid checked. vid checked. fb0, bg, and v0 are output. vid not checked. fb1, bg, and v1 are output. 1 frame figure 3.33 interlace mode display output rev. 2.0, 09/02, page 88 of 366 (5) interlace sync & video mode interlace sync & video mode is entered by se tting the scan-mode bits in the display mode register (bits scm1 and scm0 in dsmr) to b 11. this mode is for output to an interlaced display. in the case for a television tuner, the data of a single frame is divided into an even and odd field while the q2sd in interlace sync & video mode changes frames for every field. to achieve the correct composition of the window, select fb0 and fb1 which belong to one frame. since the vid is updated every field, completely different fields may be composed. it is not a problem for still images, however, moving images are not displayed correctly. the display data in the y direction only takes up half of the size set in dsy. vid on the vw screen is checked for each field. vsync bg v1 fb1 fb0 v0 v2 bg v1 fb1 ugm fb0 v0 v2 the even line data of fb0, bg, and v0 is output. the odd line data of fb1, bg, and v1 is output. the even line data of fb0, bg, and v2 is output. the odd line data of fb1, bg, and v0 is output. different images are not composed. vid checked. vid checked. vid checked. vid checked. 1 frame 1 frame after 1/30 sec figure 3.34 (1) interlace sync & video mode output rev. 2.0, 09/02, page 89 of 366 vsync bg v1 fb1 fb0 v0 v2 bg v1 fb1 ugm fb0 v0 v2 the even line data of fb0, bg, and v0 is output. the odd line data of fb1, bg, and v1 is output. the even line data of fb0, bg, and v2 is output. the odd line data of fb1, bg, and v0 is output. different images are composed. vid checked. vid checked. vid checked. vid checked. 1 frame 1 frame after 1/30 sec figure 3.34 (2) interlace sync & video mode output rev. 2.0, 09/02, page 90 of 366 3.4.4 synchronization systems the q2sd is provided with a tv sync function in addition to master mode to simplify synchronization with an external device. the tvm (tv sync mode) bits in the display register (dsmr) are used to select master mode or tv sync mode. the frame and vertical blanking flags in the status register (the frm and vbk flags in sr) are changed at detection of the vertical sync signal start position which is specified by the vsp bits in the vertical start position register ( vspr) regardless of sync mode. (1) internal synchronization mode (master mode) setting the horizontal and vertical sync signal ( +6<1& and 96<1& ) cycles and pulse widths in the display control register outputs the corresponding waveforms, and display data is output in synchronization with these signals. in interlace mode and interlace sync & video mode, a signal indicating odd field or even field is output at the 2'') pin. the ugm refreshing is performed on the basis of the +6<1& and 96<1& signals. (2) external synchronization mode (tv sync mode) in tv sync mode, the q2sd is synchronized and operated using the horizontal and vertical sync signals of a tv, vcr, or other external system in this mode, the tv, video, or other system is treated as the master, and the q2sd as the slave. synchronization is performed every horizontal scan with the (;+6<1& input signal, and every vertical scan with the (;96<1& input signal. the q2sd outputs display data on the basis of the falling edge of the (;+6<1& signal and the rising edge of the (;96<1& signal. in this mode, the horizontal sync signal, vertical sync signal, and clock from the sync signal generator should be input at the (;+6<1& , (;96<1& , and clk1 pins, respectively. the &<6,1& pin outputs a high-level signal. signals without equalizing pulses should be used for (;+6<1& and (;96<1& . in interlace mode and interlace sync & video mode, a signal indicating odd field or even field should be input at the 2'') pin. when the q2sd is operated in tv sync mode, display control register hswr, hcr, vspr, and vcr settings are essential. in non-interlace mode, the 2'') pin should be fixed high or low to prevent an unstable input level at this pin. rev. 2.0, 09/02, page 91 of 366 the q2sd performs ugm refreshing based on (;+6<1& and (;96<1& . therefore, (;+6<1& and (;96<1& must be input to enable ugm refreshing to be carried out. the signal flow in tv sync mode is shown in figure 3.35. in this mode, the cde pin can be controlled by the q2sd by comparing the colors displayed by the q2sd with the colors set in color detection registers h and l (cderh, cderl), and master r/g/b output and slave r/g/b output can be switched in pixel units by external circuitry. no matter whether display for the specified size in the q2sd is completed or not, assertion of the (;96<1& signal makes the q2sd process the vertical display completion operation and start the next screen display. when the (;96<1& signal is not asserted, the assertion of the signal is waited in the vertical blanking interval state (this is not automatically controlled). similarly, assertion of the (;+6<1& signal makes the q2sd process the horizontal display completion operation and start the next line display. when the (;+6<1& signal is not asserted, the assertion of the signal is waited in the horizontal blanking interval state (this is not automatically controlled). cpu ugm input 2 output input 1 display clock tv (sync signal generator): master field signal r, g, b clk1 r g b cde q2sd: slave master r/g/b output (input 2) and slave r/g/b output (input 1) are switched by ced figure 3.35 signal flow in tv sync mode (3) tv sync mode change procedure when b'01 is set in the tv sync mode (tvm) bits in the display mode register (dsmr) and a transition is made to synchronization system switching mode, set the display reset bit (dres) to 1 and clear the display enable bit (den) to 0 in the system control register before making the transition to synchronization system switching mode. rev. 2.0, 09/02, page 92 of 366 this procedure provides for the q2sd to perform ugm refreshing in synchron ization system switching mode. this procedure must only be carried out when the q2sd is not performing drawing. the procedure is shown below. steps 1 to 3 must be carried out in that order. 1. set bg = 0, vwe = 0, ce1 = 0, and ce2 = 0. 2. set dres = 1 and den = 0. 3. set tvm1 = 0 and tvm0 = 1. at this time, display reset is executed and the display buffer and the dbf flag is initialized to fb0 and 0, respectively. the procedure for switching from synchronization system switching mode to tv sync mode is shown in 4 to 7 below. 4. input the clock to clk1. when tvm1 = 1 and tvm0 = 0, also input signals to the (;+6<1& , (;96<1 c, and 2'') pins. 5. if the display size is to be changed, set values in the q2sd's address-mapped registers. 6. set tvm1 = 0 and tvm0 = 0, or tvm1 = 1 and tvm0 = 0, to enable clock input from the clk1 pin. if necessary, also set bg = 1, vwe = 1, ce1 = 1, and ce2 = 1. 7. set dres = 0 and den = 1. when an internal update is performed, the q2sd begins display. the relationship between the display control register settings and the display signals is shown in figure 3.36. rev. 2.0, 09/02, page 93 of 366 (when odev = 0) (interlace operation) odd field even field disp (non-interlace operation) hc hsw hde 1/2hc hds vc vsp figure 3.36 display timing rev. 2.0, 09/02, page 94 of 366 when performing display is master mode, the q2sd outputs a composite sync signal. the signal waveform is based on the falling edge of 96<1& . the low-level width of equalizing pulses and separation pulses can be set in the equalizing pulse width register (eqwr) and the separation pulse width register (spwr), respectively. hc hsw eqw equalizing pulse: 3 rasters equalizing pulse: 3 rasters equalizing pulse: 2.5 rasters separation pulse: 2.5 rasters equalizing pulse: 2.5 rasters equalizing pulse: 2.5 rasters separation pulse: 2.5 rasters equalizing pulse: 2.5 rasters separation pulse: 3 rasters equalizing pulse: 3 rasters equalizing pulse: 3 rasters separation pulse: 3 rasters spw spw (csy = 00) (csy = 10) (csy = 11) (csy = 00) (csy = 10) (csy = 11) 1/2hc 1/2hc 1/2hc eqw (interlace, first half of frame) (non-interlace operation) (interlace, first half of frame) figure 3.37 &6<1& &6<1& output waveform 3.4.5 color expansion of display screen (1) color expansion of display screen the q2sd incorporates the color palette function which can display 256 colors among 260,000 colors simultaneously. the r, g, and b have 6-bit configuration respectively, and are mapped to the q2sd register space. the color palette function performs expansion of r, g, and b, which are six bits (260,000 colors), respectively, to the specified screen among foreground, background, or cursor screen in 8 bits/pixel. the color palette is shared among these screens. rev. 2.0, 09/02, page 95 of 366 (2) color expansion of video screen when the video screen is in the ycbcr format, the q2sd performs expansion of the r, g, and b, each of 6 bits, (256,000 colors). rev. 2.0, 09/02, page 96 of 366 3.5 rendering 3.5.1 commands the q2sd performs drawing on the basis of a group of drawing commands located in the ugm. this group of drawing commands is called a display list. drawing commands comprise four- vertex screen drawing and line drawing commands which draw at rendering coordinates, and work screen drawing and work line drawing commands which draw at work coordinates. as for drawing parameter setting commands, there are register setting command and sequence control commands which control the display list such as drawing end control. line drawing, trapezoid fill, and current pointer setting commands include absolute coordinate and relative coordinate specification commands. table 3.9 lists the drawing commands. table 3.9 drawing commands type command name function four-vertex screen drawing polygon4 quadrilateral paint draws quadrilateral with four coordinates as vertices. painting can be performed with source tiling and specified color. polygon4a four-vertex screen drawing with multi-valued source as transfer source polygon4b four-vertex screen drawing with binary source as transfer source polygon4c four-vertex screen drawing using specified color line drawing line polygonal line draws solid polygonal line from start coordinates through nodal coordinates. line polygonal line drawing (absolute coordinate specification) rline polygonal line drawing (relative coordinate specification) pline polygonal line with line-type specification draws polygonal line with line type (pattern) from start coordinates through nodal coordinates. pline pattern-reference polygonal line drawing (absolute coordinate specification) rpline pattern-reference polygonal line drawing (relative coordinate specification) rev. 2.0, 09/02, page 97 of 366 table 3.9 drawing commands (cont) type command name function work screen drawing ftrap trapezoid paint performs binary eor painting of trapezoid with left side parallel to y-axis. ftrap binary eor trapezoid fill (absolute coordinate specification) rftrap binary eor trapezoid fill (relative coordinate specification) clrw rectangle zero-clear performs zero-painting of rectangle with diagonal designated by two coordinate points. work line drawing linew polygonal line draws solid polygonal line from start coordinates through nodal coordinates. linew binary polygonal line drawing (absolute coordinate specification) rlinew binary polygonal line drawing (relative coordinate specification) register move current pointer setting (absolute coordinate specification) setting rmove current pointer setting (relative coordinate specification) lcofs local offset value setting (absolute coordinate specification) rlcofs local offset value setting (relative coordinate specification) sclip sets rectangle with diagonal designated by origin and specified coordinate point as clipping area. uclip sets rectangle with diagonal designated by two coordinate points as clipping area. wpr sets a specific address-mapped register. sequence jump command sequence jump (branch) control gosub subroutine call (branch). nesting depth is one. ret subroutine return nop3 no operation: no processing executed. vbkem waits until the next vertical blanking interval. drawing end trap ends drawing processing and generates cpu interrupt. rev. 2.0, 09/02, page 98 of 366 reference (c) work drawing example (polygon) (a) 4-vertex drawing example source coordinates rendering coordinates rendering coordinates drawing work coordinates (b) line drawing example drawing rendering coordinates drawing drawing work coordinates (d) work drawing example (line) drawing dxl a b f b b c c d d e a a c d e f a b c figure 3.38 drawing functions 3.5.2 image data reference the q2sd can perform color-drawing while referring to the source data, or cutting-out drawing while referring to the work data. among the q2sd commands, the commands that refer to the source data are pol ygon4a, polygon4b, pline, and rpline. the co mmands that refer to the color data that is included in the command parameter are pol ygon4c, line, rline, linew, and rlinew. commands that refer to the binary-value work data are pol ygon4a, polygon4b, and polygon4c. the co mmands that create the binary work data are ftrap, rftrap, linew, rlinew, and clrw. the reference to the binary work data can be performed simultaneously with the reference to the source data or the color data. there are two types of source data: multi-valued source data or binary source data. rev. 2.0, 09/02, page 99 of 366 polygon4a polygon4b polygon4b polygon4c destination applicable command transparent mode specified color data non-transparent mode transparent mode multi-valued source data binary source data polygon4a polygon4b polygon4b polygon4c color 0 color 1 color 1 color figure 3.39 example of polygon4 transfer data combinations (1) multi-valued source data multi-valued source data is defined as multi-valued source coordinates (2-dimensional coordinates). however, the horizontal width (tdx) is specified as a value of 8 pixels or more. the configuration of multi-valued source data is shown in figure 3.40. in a linear arrangement (lni = 1), a multiple of 8 pixels should be set as the tdx value. for the multi-valued source data, either 8 bits/pixel or 16 bits/pixel can be selected. when 8 bits/pixel is used, the lower bytes are the smaller side of the source coordinate x, and the higher bytes are the larger side of the source coordinate x. rev. 2.0, 09/02, page 100 of 366 8-bit or 16-bit data multi-valued coordinates higher byte lower byte 8-bit/pixel data y x tdx figure 3.40 multi-valued source data configuration (2) binary source data binary source data is arranged in linear fashion in the binary source area in the ugm, and is managed as 2-dimensional coordinates (binary source coordinates) by tdx and tdy in the polygon4b co mmand. the left-hand screen pixel must be located at the lsb of the binary source data when the binary source data area is viewed from the q2sd. however, the horizontal width (tdx) is specified as a multiple of 8 pixels. an example of binary source data is shown in figure 3.41. a binary source is used for the definition of character data and line-type data. when drawing, 0s are converted to color0 data, and 1s to color1 data (in transparent mode, only 1s are converted to color1 data for drawing). tdy tdx lsb lsb msb example of kanji font as binary source tdx = 24, tdy = 24 data: h'1c00, h'0e07, h'430c, h'0c1c, h'd8e3, h'ffff, h'0c00, h'0003, h'030c, h'0140, h'4718, h'3fff, h'636e, h'2c18, h'1863, h'6320, h'3018, h'1fff, h'6310, h'1800, h'1860, h'ff98, h'0c3f, h'0060, h'600f, h'ec60, h'ffff, h'b00c, h'0c01, h'0338, h'1c0c, h'0c0e, h'3c0e, h'038c, h'ecf8, h'6000 binary source coordinates figure 3.41 example of kanji font as binary source (tdx = 24, tdy = 24) rev. 2.0, 09/02, page 101 of 366 (3) specified color data specified color data is defined directly by drawing parameter color specifications (color, color0, color1, line color0, and line color1). when the q2sd is used for 8- bit/pixel operation, the same color palette number is defined in the upper 8 bits and lower 8 bits in the drawing parameter color specification. when the q2sd is used for 16-bit/pixel operation, the r, g, and b values are defined directly by the drawing parameter color specification. however, with linew and rlinew, the value to be drawn at work coordinates is defined by the rendering attribute eos bit. (4) binary work data binary work data is defined as binary work coordinates (2-dimensional coordinates). work data is used to implement polygon painting. polygon outline data is created with the ftrap command, etc., and the created figure data is used to delineate the rendering figure. if, for example, the polygon4c co mmand is used jointly for work, the work area polygon can be drawn in the rendering area with the specified color value. the configuration of binary work data is shown in figure 3.42. lsb y msb x number of pixels specified by mwx bit (512/10 23 ) binary work coordinates figure 3.42 binary work data configuration 3.5.3 rendering attributes thirteen kinds of attribute specifications can be made: work (work), clipping (clip), transparent (trns), source style (styl), net drawing (net), source half (half), even/odd select (eos), bold line drawing (fwul, w2ul, fwdr, w2dr), source linear address (lni), 4-pixel-unit processing (fst), source coordinate relative address (rel), edge (edg), and color offset (coof). the attributes that can be specified depend on the command. the rendering attributes are embedded in the commands, and can be specified on an individual command basis. figure 3.43 shows the bit arrangement for rendering attributes. rev. 2.0, 09/02, page 102 of 366 15 0 11 10 draw mode code trns styl clip net 0 lni eos work fst trns styl clip net rel 1 eos work 0 trns styl clip net rel eos work trns 0 clip net rel eos eos work clip net eos work fst clip edg clip eos clip trns 1 clip net w2ul 0 coof coof half fwdr eos w2dr fwul net rel clip eos edg1 edg2 1 polygon4a polygon4a polygon4b polygon4b polygon4c ftrap, rftrap linew, rlinew line, rline pline, rpline jump, gosub clrw (commands other than the above) note: shaded areas should be cleared to 0. fwul, w2ul, fwdr, w2dr: bold line drawing bits rel: relative address specification edg: edge drawing bit figure 3.43 rendering attribute bit arrangement (1) transparency sp ecification (t rns) when color expansion of binary source data is performed, transparency or non-transparency can be selected on an individual drawing command basis with the trns bit. when transparency is selected, a 0 in the binary source data is transparent and a 1 has the value of the color1 parameter. when non-transparency is selected, a binary data 0 has the value of the color0 parameter, and a 1 has the value of the color1 parameter. with multi-valued source data, all-0 data becomes a transparent color, and those pixels are not drawn. the transparency specification can be used with the polygon4a, polygon4b, pline, and rpline co mmands; in other commands, the trns bit should be cleared to 0. (2) source style specification (styl) when drawing a rectangle, the styl bit can be used to select, on an individual drawing command basis, whether the source data is to be enlarged or reduced, or referenced repeatedly. if no style specification is made, the source data is enlarged or reduced in proportion to the size of the rendering area. when a style specification is made, the source data is referenced repeatedly in proportion to the size of the rendering area. this attribute is therefore used when drawing repeated patterns such as hatch patterns. the source style specification can be used with the polygon4a, polygon4b, pline, and rpline co mmands; in other commands, the styl bit should be cleared to 0. when a source style specification is used, do not make a source half specification. an example of a source style specification is shown in figure 3.44. rev. 2.0, 09/02, page 103 of 366 no style specification (styl = 0) style specification used (styl = 1) example of enlarged by factor of 2 referenced twice source data drawing data figure 3.44 example of source style specification (3) clipping specification (clip) the q2sd can perform clipping area management. in the clipping area, drawing is performed. outside the clipping area, only operations are performed although the results are not written to memory. there are two kinds of clipping area: a system clipping area designated by the sclip command, and a user clipping area designated by the uclip command. the system clipping area has a fixed drawing range. the system clipping area is always valid, regardless of attribute specifications. a user clipping area can be designated as desired within the system clipping area. whether or not clipping is performed in that area can be selected on an individual command basis with the rendering attribute clip bit. the boundary is drawn. clipping is set in the screen coordinates without offset. figure 3.45 shows an example of the clipping specification. rev. 2.0, 09/02, page 104 of 366 an example of a clipping specification is shown in figure 3.42. clip bit = 1 clip bit = 0 system clipping area designated user clipping area (359,239) (0, 0) rendering coordinates without offset work coordinates without offset figure 3.45 example of clipping specification (4) net drawing specification (net) the net bit can be used to select, on an individual drawing command basis, whether or not net drawing is to be performed. net drawing is a function for drawing only pixels at coordinates for which the condition rendering coordinates x + y = eos (0: even number, 1: odd number) is true. for example, if eos = 0, drawing will only be performed at coordinates y = 0, x = 0, 2, 4, 6, 8, ..., y = 1, x = 1, 3, 5, 7, 9, ... . this function enables the drawn figure and ground to be mutually semi-composed. the net drawing specification can be used with the pol ygon4 co mmands, and the line, rline, pline, and rpline commands; in other commands, the net bit should be cleared to 0. (5) even/odd select specification (eos) even pixels are selected when eos = 0, and odd pixels when eos = 1. the even/odd select specification is used together with the net specification or source half specification. with the linew and rlinew commands, drawing is performed at the work coordinates with 0 when eos = 0, and with 1 when eos = 1. examples of even/odd select specifications are shown in figure 3.46. rev. 2.0, 09/02, page 105 of 366 even-number referencing with half drawing specification (half = 1, eos = 0) source data starting point drawing data odd-number referencing with half drawing specification (half = 1, eos = 1) figure 3.46 examples of even/odd select specifications (6) source half drawing specification (half) the half bit can be used to select whether all or only half of the source data is to be referenced. when the source half drawing specification is selected, only eos (0: even number, 1: odd number) data is referenced from the source starting point. thus only half of the source data in the horizontal direction is referenced. the source half drawing specification can only be used with the pol ygon4b (binary source) command; in other commands, the half bit should be cleared to 0. when a source half specification is used, do not make a source style specification. do not use this specification when the x coordinate of the drawing coordinates is within a negative range since the drawing image may be distorted. (7) work specification (work) when drawing is performed at rendering coordinates with pol ygon4 co mmands, the work bit can be used to select, on an individual drawing command basis, whether or not binary work data is to be referenced. when binary work data referencing is selected, drawing is performed if the work data for the pixel corresponding to the rendering coordinates is 1, but not if the work data is 0. the same shape as that drawn at work coordinates can thus be drawn at rendering coordinates. drawing at work coordinates can be performed either by means of the ftrap command or else by the superh. ensure that ugm drawing access by command and ugm drawing access by the superh are not performed simultaneously. the work specification can be used with the polygon4a, polygon4b, and polygon4c co mmands; in other commands, the work bit should be cleared to 0. with the pline and rpline commands, this attribute is specified but work references are not performed. rev. 2.0, 09/02, page 106 of 366 (8) bold line drawing specification taking individual line segments of a polygonal line specified by parameters as reference lines, this specification makes the reference lines bold lines in the upper-left direction and lower-right direction, independently. whether or not this attribute is enabled is specified by the fwul bit and fwdr bit, while the width of a bold lines can be selected from line widths 1 to 5 by a combination of bits w2ul and w2dr. the fwul bit enables bold-line implementation in the upper-left direction, while the fwdr bit enables bold-line implementation in the lower-right direction. the w2ul bit is valid when fwul = 1, and the w2dr bit when fwdr = 1. this function is valid for each segment of a polygonal line. using the segment line main scanning axes, lines with the same slope in the up (left) and down (right) directions, and of the same length, are drawn repeatedly. therefore, the shape of the segment linkage parts is not considered. this function can be used with the line and rline commands; in other commands, the fwul, w2ul, fwdr, and w2dr bits should all be cleared to 0. when performing bold line drawing, set the vertex coordinates so that the entire bold line area does not extend beyond the drawing area (both x and y in the range C2045 to 2044). table 3.10 bold line drawing settings fwul w2ul fwdr w2dr line width (direction, magnification) 0 0 0 0 1 (no magnification) 1 1 (no magnification) 1 0 2 (lower right 1) 1 3 (lower right 2) 1 0 0 1 (no magnification) 1 1 (no magnification) 1 0 2 (lower right 1) 1 3 (lower right 2) 1 0 0 0 2 (upper left 1) 1 2 (upper left 1) 1 0 3 (upper left 1, lower right 1) 1 4 (upper left 1, lower right 2) 1 0 0 3 (upper left 2) 1 3 (upper left 2) 1 0 4 (upper left 2, lower right 1) 1 5 (upper left 2, lower right 2) rev. 2.0, 09/02, page 107 of 366 (a) when dx 3 dy (b) when dx < dy (a) when dx 3 dy (b) when dx < dy reference line 1. upper-left magnification 1 (w2ul = 0), lower-right magnification 2 (w2dr = 1) 2. upper-left magnification 2 (w2ul = 1), lower-right magnification 1 (w2dr = 0) dx dx dx dy dy dy dx dy figure 3.47 examples of bold line drawing (9) source address linear specification (lni) use of a 2-dimensional virtual address or a linear address as the source address can be selected, on an individual drawing command basis, by means of the lni bit. to use a linear address, set this bit to 1. this function can be used with the polygon4a co mmand; in other commands, the lni bit should be cleared to 0. for details of command operation, see section 4.1.1, pol ygon4a. (10) 4-pixel-unit processing (fst) whether or not 4-pixel unit processing is performed can be specified for individual drawing commands by means of the fst bit. to perform 4-pixel unit processing, set the fst bit to 1. in this case, no other rendering attributes except clip can be used. this function can be used with the polygon4a and polygon4c co mmands; in other commands, the fst bit should be cleared to 0. rev. 2.0, 09/02, page 108 of 366 when using this attribute, set the command parameters as indicated in the individual command descriptions. (11) source coordinate relative address specification (rel) setting the rel bit to 1 in pol ygon4a, polygon4b, jump, and gosub co mmands enables source referencing and branching to be performed at an address relative to (before or after) the command code. the source address must be a linear address. also, for reasons relating to referencing of a multi-valued source arranged in linear fashion, the lni bit must be set to 1 when using polygon4a; oper ation cannot be guaranteed if the lni bit is 0. the command code address is the relative address origin. (12) edge drawing (edg) with the ftrap and rftrap commands, setting the edg bit to 1 enables edge lines to be drawn after completion of trapezoid painting. whether edge line drawing is performed with 0 or with 1 is specified by the eos bit. (13) line drawing edge specification (edg1, edg2) whether or not edge drawing is performed for a polygonal line with line type can be specified for individual drawing commands by means of the edg1 bit. this function is valid for each segment of a polygonal line. using the segment line main scanning axes, solid lines with the same slope and of the same length, are drawn either vertically or horizontally. therefore, the shape of the polygonal line linkage parts is not considered. the solid edge lines have the value of color1. this function can be used with the pline and rpline commands; in other commands, the edg1 bit should be cleared to 0. a source size of 8 or 16 can be used. set 8 or 16 for source size parameter tdx. rev. 2.0, 09/02, page 109 of 366 edge drawing 1 specification (edg1 = 1) x-axis main scan drawing y-axis main scan drawing reference line whether or not edge drawing is performed for a polygonal line with line type can be specified for individual drawing commands by means of the edg2 bit. this function is valid for each segment of a polygonal line. here, each segment of the polygonal line specified by the parameter is considered as a reference line. this function is implemented for each segment of a polygonal line, using the following procedure. first, the reference line is drawn as a line with line type. next, using the segment line main scanning axes, solid lines with the same slope and of the same length, are drawn either vertically or horizontally. finally, the reference line is drawn as a solid line. therefore, the shape of the polygonal line linkage parts is not considered. the solid line drawn last has the value of color1. this function can be used with the pline and rpline commands; in other commands, the edg2 bit should be cleared to 0. edge drawing 2 specification (edg2 = 1) x-axis main scan drawing y-axis main scan drawing reference line rev. 2.0, 09/02, page 110 of 366 both the edg1 and edg2 bits should not be set to 1 at the same time. (14) color offset (coof) this function can be used with the polygon4a co mmand. in 16-bit/pixel drawing, if the rendering attribute c oof bit is set to 1, the result of adding the value in the color register to the value of the multi-valued source data is drawn. the operation is performed by saturation processing. in 8-bit/pixel drawing, the c oof bit must be cleared to 0. use 100% or enlarged drawing since miniaturized drawing of the source may distort the image. 3.5.4 command fetching (1) command fetch operation when the rendering start bit rs in the system control register sysr is set to 1, the q2sd fetches the display list in the ugm to carry out drawing oper ations. the display list and the source data to be used by the display list should be stored in the ugm before the q2sd starts to fetch the display list by the rendering start bit. the q2sd performs sequential fetches in low-to-high address order, starting at the address set in the display list start address register (dlsar). the fetch address can be changed midway, using a jump or gosub co mmand. q2sd fetching can be terminated by placing a trap command at the end of the display list. the q2sd has a dedicated command buffer, and an equivalent area of the ugm is accessed at one time. when processing of the commands in this buffer is completed, another command fetch is performed. if the commands include a jump, gosub, or other co mmand that changes the flow, the q2sd starts fetching again from the new address indicated by that command. figure 3.48 shows an example of the display list. rev. 2.0, 09/02, page 111 of 366 dlsar command sequence 2 trap gosub subroutine ret command sequence 1 jump (subroutine depth is limited to one level) figure 3.48 example of display list (2) drawing suspension and resumption the q2sd supports a drawing suspend/resume function, synchronized with the 96<1& signal between the cpu and q2sd. this enables multiple drawing processing to be performed in parallel with priority order. this function is mainly used when alternately using frame buffers and the background screen to execute drawing. rev. 2.0, 09/02, page 112 of 366 interrupt generated by q2sd interrupt generated by q2sd frame buffer drawing background screen drawing q2sd drawing processing cpu processing background screen drawing vbk = 1 rbrk = 1 brk = 1 rs = 1 rs = 1 tra = 1 interrupt acceptance drawing suspension command interrupt acceptance interrupt drawing drawing resumption figure 3.49 example of timing for suspending and resuming background s creen drawing (3) suspension processing 1. set brcl to 1 in the status clear register (srcr), clear the brk bit to 0 in the status register (sr), and set the drawing suspension directive bit (rendering break: rbrk) to 1 in the system control register ( sysr). 2. next, monitor the brk bit and tra bit. 3. when brk is observed to be set to 1, this means that the currently executing drawing command processing has ended and the drawing unit has halted (drawing has been suspended) at the point at which the next drawing command was fetched. information required for software processing in anticipation of resumption processing should be read from the address-mapped registers and saved in memory. at this time, the rbrk bit is cleared to 0. 4. when tra is observed to be set to 1, this means that a trap command has been executed and q2sd drawing processing has ended. therefore, ensure that no subsequent resumption processing is carried out. if drawing is to be performed after suspension processing, wait until the tra flag is observed to be set to 1. rev. 2.0, 09/02, page 113 of 366 (4) resumption processing 1. the parameters saved immediately after suspension are restored. some are written directly to the registers, and some are set by command. the former include the subroutine return address (which can also be set with the wpr command), and the latter, clip area, local offset, current pointer, and execution restart addresses. of the latter, the execution restart address is restored by setting the command status register value at the time of the suspension as the jump destination of a jump co mmand. for the other parameters in the latter group, settings should be made to provide for recovery by means of the appropriate command before execution of this jump co mmand. 2. after performing a write for the purpose of subroutine return address restoration, and creating a command list to restore the other parameters, drawing can be resumed by setting the address of this command list in dlsar and implementing a rendering start. 3.5.5 internal buffer the q2sd has three internal buffersa command buffer, source buffer, and work bufferas shown in figure 3.50. a ugm q2sd command buffer a ? b source buffer c ? d work buffer e ? f b command buffer size command buffer size display list c d source buffer size source buffer size binary source coordinates or multi-valued source coordinates e f work buffer size work buffer size binary work coordinates figure 3.50 updating of q2sds internal buffers rev. 2.0, 09/02, page 114 of 366 these buffers are used by the q2sd to temporarily store data held in the ugm. the q2sd uses the data stored in these buffers when executing drawing. the functions of these buffers are as follows: 1. command buffer (32 bytes 2) used by the q2sd to store a display list held in the ugm. the buffer s ize is 64 bytes. 2. source buffer (64 bytes) used by the q2sd to store a binary source or multi-valued source held in the ugm. the buffer size is 64 bytes. 3. work buffer (16 bytes) used by the q2sd when performing drawing at binary work coordinates in the ugm. the buffer size is 16 bytes. when buffer contents are not updated, (when the same address is referenced by data of or below the capacity of the buffer, or a reference ends at a location at or below the capacity of the buffer from the previous reference start location), the previous buffer contents will be used even though the data in the ugm is rewr itten. to intentionally update buffer contents, the address of a location exceeding the buffer capacity should be referenced. 3.6 video capture the q2sd can incorporate a yuv 4:2:2 8-bit d ata stream obtained by digital encoding of ntsc signals. the captured data is displayed on the video screens. 3.6.1 configuring circuit for video capture (1) video capture operation video capture is performed at the rising edge of the vqclk signal. the 8-bit data stream corresponding to the number of pixels set in the vsizex field in the video window size register (vsizer) is captured for each vhs signal and transferred to one of three video storage areas determined by video area start address registers ( vsar). these areas are used sequentially in frame units. the video window status bits (vid0, vid1) are valid when 0 is set in the video incorporation enable bit (vie) and indicate the most recent video area in which video capture has been completed. the size of the video storage areas is determined by vsizex and vsizey. use a frequency not exceeding 1/2 the system operating clock frequency for vqclk (the system operating clock should be in the range 64 to 66 mhz). a number of vqclk cycles equal to twice the number of luminous pixels are necessary per vhs. 996 , 9+6 , 92'' and vqclk are accepted following hardware reset release, and video capture is started by setting vie to 1, having the first vvs signal sync signal input, then having the first vhs signal sync signal input. rev. 2.0, 09/02, page 115 of 366 as the video storage area capture line number is incremented each time a vhs signal sync signal is input, vqclk must not be input during the vhs signal sync signal period. the vqclk pin should be low level except when a valid data is output. for video capture, select a ugm bus width of 32 bits by s etting mes1 and mes0 in the memory mode register (memr). the relationship between video input signals is shown in figures 3.51 and 3.52. cb0 y0 cr0 y1 cb2 y2 vin7 to vin0 vqclk # # cr2 y3 figure 3.51 video incorporation signals vvs vhs vodd qclk - 2h t vhs t vos t hqs - 1h 1/ 2 3/ 4 5/ 6 7/ 8 9/ 10 11/ 12 13/ 14 vd[15:8] (field) synchronization period the vqclk signal should not be input during this period. capture is possible. (vqclk) figure 3.52 video capture timing (2) video capture and display operation as the data (which supports to the 8-bit ycbcr (2:2:1) format specified in itu-601) arrives from the video decoder, the video-capture function writes it to the video-capture area in the ugm. three areas, v0, v1, and v2, are captured in the order and video display from an area may commence once the operation of writing to that area has been completed. rev. 2.0, 09/02, page 116 of 366 the current area for writing is automatically switched when the capture of data for one area has been completed. capture display v0 v0 v1 v2 v0 v1 v2 v0 v1 v2 v0 v1 v2 v0 v1 v2 v0 figure 3.53 capture state the functions of displaying and capturing video data are each capable of independent operation since the q2sd is able to capture video data whether the display is on or off; that is,. using the three areas makes it possible to deal with the situation where the times at which capture and display start are not synchronized and thus do not necessarily match. while video capture is in progress (vie = 1), display of the area specified by the immediately prior value of the vid bits commences. when a capture operation stops while it is in progress, the current screen continues to be displayed, as is shown in figure 3.54. when the capture operation is resumed, the current screen will continue to be displayed until the vid bits are updated on completion of the capture of one screen. setting the vie bit to 1 resets the video capture area to v0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . capture updating vid display capture stopped capture resumed v0 v1 v2 00 01 10 v0 v1 00 01 00 v0 v1 v0 v1 v2 v0 v0 v0 v0 figure 3.54 display state 3.6.2 video capture mode the mode of capture by the q2sd is selectable from among four modes. the appropriate mode is selected by such factors as the resolution of the video screen, the output format of the video decoder, and the destination device (crt, lcd, tv, etc.) for the output signal. rev. 2.0, 09/02, page 117 of 366 when oden1, oden0 = 0, 1, a one-frame screen is created by combining even and odd fields. motion interpolation is not performed. in the case of moving pictures with violent motion, the screen may be difficult to see as a still picture. this mode is suitable for interlace display under conditions in which the frame rate and the number of scanning lines in the vertical direction are both the same as for the input video. line 1 is line 0 of the ugm to support the case that the original signal has no line 0. note that even and odd lines are reversed between the original signal and the ugm. therefore, capture begins with an odd f ield (vinm = 0) when an even field is displayed first within a frame (odev = 1), and with an even field (vinm = 1) when an odd field is displayed first within a frame (odev = 0). when oden1, oden0 = 1, 0, or 1, 1, a one-field image is treated as a one-field image. at this time, the number of vertical scanning lines is halved. original-size display is not possible. to preserve the vertical/horizontal ratio, the horizontal multiplication factor should be adjusted. this mode is used for non-interlace (scm1, 0 = 0:0) display. set the value of vactive according to the setting of oden1 and oden0 in the video incorporation mode register (vimr). when performing video capture, input the video stream data to the vin pin, without having scaling processing (thinning-out processing) performed by the video stream decoder. 1. when oden1 = 0 and oden0 = 1 make the value of vactive the total number of effective display lines in the vertical direction in two 2 996 intervals. for example, with 240 effective display lines in the vertical direction in one 1 996 interval, the setting should be: vactive = 240 2 = 480 2. for settings other than oden1 = 0, oden0 = 1 make the value of vactive the number of effective display lines in the vertical direction in one 1 996 interval. rev. 2.0, 09/02, page 118 of 366 video data display size video screen area video stream decoder hactive q2sd vsizex vqclk vin7Cvin0 vactive vsizey ugm vsizex: horizontal reduction (thinning-out) ratio set by video incorporation reduction ratio (1/1, 1/2, 1/3, 1/4, or 1/6) vsizey: vertical reduction (thinning-out) ratio set by video incorporation reduction ratio (1/1, 1/2, 1/3, or 1/4) hactive (pixels) 3 vsizex vactive (pixels) 3 vsizey vqclk high-level width (sec.) 3 mclk = clk0 n (hz) clk0: frequency (hz) of clock input to clk0 pin n: multiplication factor determined by pins mode2 to mode0 2 mclk figure 3.55 video screen area (3) non-interlace mode capture (oden1 = 0, oden0 = 0) this is the appropriate mode when the video decoder is in non-interlace mode. all video data for each vsync signal is stored in a single capture area. when the output of the video decoder is in interlace sync mode, take care with regard to the size of the capture area taken up by the captured data, since the data consists of only half of the lines for the screen. rev. 2.0, 09/02, page 119 of 366 v0 v2 v1 capture area video decoder output figure 3.56 interlace capture (4) interlace composite capture (oden1 = 0, oden0 = 0) this mode is applicable to video data for an interlaced display. data for the odd and even fields are composed and stored in a single capture area. when the signal output by the video decoder is not for an interlaced display, correct operation is not guaranteed. v0 v1 v0 odd field capture area video decoder output even field composite figure 3.57 interlace composite capture (5) interlace capture (odd field only: oden1 = 1, oden0 = 0) this stores the odd fields of data for an interlaced mode display (the vodd signal is at its low level) in a single capture area. take care with regard to the size of the capture area taken up by the captured data, since the data consists of only half of the lines for the screen. when the output of the video decoder is in non-interlace sync mode, every second field of data will not be stored. the data size for capture, however, are the same. rev. 2.0, 09/02, page 120 of 366 v0 odd field capture area this field is not captured. video decoder output this field is not captured. figure 3.58 interlace capture (odd field) (6) interlace capture (even field only: oden1 = 1, oden = 1) this stores the even fields of data for an interlaced mode display (the vodd signal is at high low level) in the capture area. take care with regard to the size of the capture area taken up by the captured data, since the data consists of only half of the lines for the screen. when the output of the video decoder is in non-interlace sync mode, every second field of data will not be stored. the data size for capture, however, are the same. v0 v1 even field even field capture area this field is not captured. video decoder output figure 3.59 interlace capture (even field) (7) field order for video capture the field order for video capture is specifiable by the video incorporation mode bit (vinm) in the video incorporation mode register (vimr). this enables to assign the first field to either the rev. 2.0, 09/02, page 121 of 366 upper or lower line. motion interpolation is not performed. in the case of moving pictures with violent motion, the screen may be difficult to see as a still picture. when the first field is an odd field and the second field is an even field, clear the vimm bit to 0. (the odd and even fields belong to the same frame.) video input decoder (video decoder output) when the first field is an even field and the second field is an odd field, set the vimm bit to 1. (the odd and even fields belong to the same frame.) when oden1 = 0 and oden0 = 1 (composite and capture), the first field is stored in an even line and the second field is stored in an odd line. video area (ugm) when oden1 = 0 and oden0 = 1 (composite and capture), the first field is stored in an even line and the second field is stored in an odd line. video capture video capture when oden1 = 1 and oden0 = 0 (odd field capture), odd fields (first field) are stored sequencially. when oden1 = 1 and oden0 = 0 (odd field capture), odd fields (second field) are stored sequencially. when oden1 = 1 and oden0 = 0 (even field capture), even fields (second field) are stored sequencially. when oden1 = 1 and oden0 = 0 (even field capture), even fields (first field) are stored sequencially. 1 3 5 7 477 479 0 2 4 6 476 478 0 2 4 6 476 478 1 3 5 7 477 479 1 0 1 2 3 4 5 6 7 476 477 478 479 0 1 2 3 0 1 2 3 0 1 2 3 4 5 6 7 476 477 478 479 238 239 238 239 0 1 2 3 0 1 2 3 238 239 238 239 0 3 2 5 4 7 479 478 477 478 0 1 2 3 4 5 6 7 6 478 479 476 477 1 3 5 7 477 479 0 2 4 6 476 478 1 3 5 7 477 479 0 2 4 6 476 478 figure 3.60 interlace video input field handling specification rev. 2.0, 09/02, page 122 of 366 3.6.3 reduction of video capture images the size of the captured image may be reduced by setting bits vsiz0 to vsiz4 in the video capture mode register (vimr), where vertical and horizontal reduction ratios are independently specifiable. the selectable reduction ratios in the horizontal direction are 1/2, 1/3, and 1/4 and the ratios in the vertical direction are 1/2, 1/3, and 1/4. the vsizex and vsizey bits should be set to the value obtained that the number of horizontal/vertical valid pixels is multiplied by the video incorporation reduction ratio (vsiz4 to vsiz0) and the result is rounded down to 0. 1 1/4 120 1/3 160 1/2 240 vsizey 480 vsizex 640 1/6 106 1/4 160 1/3 212 1/2 320 1 when data of 640 480 is captured from a video decoder figure 3.61 reducing the size of the captured image as an example, when the setting of the vsizex bits is 480 and the setting for the reduction ratios is as above, each current frame of data in the memory is displayed on a video-screen area which is wider than 320 pixels since video data is not sent for the horizontal pixel range from 321 to 480. on the other hand, when the setting of the vsizex bits is 240, which is smaller than the captured image, the data which is displayed will be cut off since there is no screen area for the horizontal pixel range from 241 to 320. rev. 2.0, 09/02, page 123 of 366 320 480 240 480 320 240 240 200 the system attempts to display data which is not being captured (the corresponding current area is displayed). when horizontal and vertical reduction ratios of 1/2 are set for 640 480 pixel data and both the vsizex and vsizey bits are set to 480 when horizontal and vertical reduction ratios of 1/2 are set for 640 480 pixel data and the respective settings for the vsizex and vsizey bits are 240 and 200 the data of this area is not captured. figure 3.62 incorrect settings for the reduction ratios these failures will occur with incorrect setting of the vsizey bits. when the result of a reduction calculation is non-integer or odd, the result is rounded off to obtain an even number. example: size of data to be sent by video decoder reduction ratio = video window size x: 640 1/3 = 213.3333 ? 212 y: 480 1/3 = 160 3.6.4 setting video capture position the method of address calculation is shown below. rev. 2.0, 09/02, page 124 of 366 0000000000 000000000 1514131211109876543210 1514131211109876543210 vsah vsal 0000 00000 1211109876543210 9876543210 0000000000 000000000 1514131211109876543210 1514131211109876543210 vsah vsal 0000 00000 11109876543210 109876543210 coordinates when mwx = 0 (512) coordinates when mwx = 1 (1024) x coordinate y coordinate x coordinate y coordinate figure 3.63 setting up the capture area within the range of the ugm, any mu ltiple of 16 is specifiable as the y coordinate and any multiple of 64 is specifiable as the x coordinate. note that the specified area is accessed as 16- bit/pixel data. therefore, when the video screen overlaps with the foreground or background screen, the area of overlap is also accessed as 16-bit/pixel data. when the mwx bit is specified as 0 to select the 512-pixel mode, the values for the y coordinate are from 0 to 8176 (pay attention to the setting for memory) and values for the x coordinate are from 0 to 960 (actually, the values which exceeds 511 should not be specified); y coordinates are specified as integer multiples of 16 and x coordinates are specified as integer multiples of 64. when the mwx bit is specified as 1 to select the 1024-pixel mode, the values for the y coordinate are from 0 to 4080 and the values for the x coordinate are from 0 to 1984 (actually, values which exceed 1023 should not be specified); y coordinates are specified as integer multiples of 16 and x coordinates are specified as integer multiples of 64. the value of the video window size in the x direction (vsizex) is up to 640. an example of the calculation of the video area is given below. when the mwx bit specifies 512-pixel mode and three video screens are allocated, as is shown in figure 3.64, the settings of each of vsah and vsal registers are as given below. rev. 2.0, 09/02, page 125 of 366 0 112 119 208 231 327 119128 247256 375 511 v0 fg bg v1 v2 figure 3.64 example of the settings for capture areas v0: x = 0, y = 0 y coordinate: 0000000000000, x coordinate: 00000000000 vsa: 0000000000000000, 0000000000000000 vsah0: h 0000, vsal0: h 0000 v0: x = 128, y = 112 y coordinate: 0000001110000, x coordinate: 00010000000 vsa: 0000000000000001, 1100010000000000 vsah0: h 0001, vsal0: h c400 v0: x = 256, y = 208 y coordinate: 0000011010000, x coordinate: 00100000000 vsa: 0000000000000011, 0100100000000000 vsah0: h 0003, vsal0: h 4100 3.6.5 format of captured data the q2sd video input interface supports the 8-bit ycrcb pixel-stream format. table 3.11 shows the configuration of the q2sds pins and the correspondence between the q2sd pins and the bits of y, cr, and cb data. figure 3.65 shows the flow of data from a video decoder. a video signal according to the ntsc specification consists of the y, or luminance, signal (monochrome signal) and the c, or chrominance, signal (color signal)this was chosen to retain compatibility with monochrome broadcasting. the result of the sampling of these signals by a video decoder is the quantized data. rev. 2.0, 09/02, page 126 of 366 since the ntsc specification is based on the nature of the human eye, which is less sensitive to chrominance than to luminance, chrominance is only represented by half as many bits as luminance. only half as many bits are thus sampled from the c signal as from the y signal, and the same proportion applies to the data. furthermore, the c data is also divided into red and blue components, i.e., cr (red - y) and cb (blue - y). the final result is thus ycbcr data. figure 3.66 depicts the data for one pixel. table 3.11 8-bit pixel interface q2sd vin7 vin6 vin5 vin4 vin3 vin2 vin1 vin0 y datay7y6y5y4y3y2y1y0 c data cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 cb7 cb6 cb5 cb4 cb3 cb2 cb1 cb0 0 15 y0 image data (1st word) 87 cb0 y1 image data (2nd word) cr0 y2 image data (3rd word) cb2 y3 image data (4th word) cr2 yn-1 image data (nth word) crn/4 data flow n = even number figure 3.65 the flow of ycbcr (4:2:2) data rev. 2.0, 09/02, page 127 of 366 two pixels of data are processed as a single item of information in the ycbcr format. one pixel of data consists of the components shown below. 1 pixel = y (8 bits) + cb (4 bits) + cr (4 bits) = 16 bits the ration of the respective amounts of data is thus 2:1:1. since two pixels of data are sent in each transmission as described above, the ratio is in fact 4:2:2. 1 pixel cr: 8 bits y: 8 bits cb: 8 bits 1 pixel y: 8 bits figure 3.66 ycbcr (4:2:2) data format although yuv and yc d ata differ in terms of the range used to represent the data (notation), the same formula, which conforms with ccir-601, is applied in converting both into rgb format. yuv d ata is represented by values in the range from 0 to 1 while yc data is represented as 8-bit data. when yuv for mat: luminance: y: 0 to 1, chrominance: u: - 0.5 to + 0.5, v: - 0.5 to + 0.5 rbg: r: 0 to 1, g: 0 to 1, b: 0 to 1 when yc format: luminance: y: 16 to 235 u: 16 to 240 v: 16 to 240 chrominance: cb: - 112 to 112* cr: - 112 to 112* rbg: r: 16 to 235 g: 16 to 235 b: 16 to 235 note: * when data is input to the q2sd video capture input, the value ranges from 16 to 240 because offset of 128 is added. ycbcr - rgm conversion formula r = y + (cr - 128) 1.37 g = y - 0.698 (cr - 128) - 0.036 (cb - 128) b = y + (cb - 128) 1.73 where y ranges from 16 to 235, cr ranges from 16 to 240, and cb ranges from 16 to 240. 3.6.6 ycbcr and rgb data the q2sd has two circuits which convert ycbcr data into 16-bit rgb data as shown in figure 3.67. use either of them. when rgb = 1, select vwry = 0. when rgb = 0, select vwry = 1. rev. 2.0, 09/02, page 128 of 366 ycbcr data (video capture) rgb = 1 ugm rgb = 0 vwry = 1 ycbcr/rgb conversion circuit rgb data (display) vwry = 2 ycbcr/rgb conversion circuit figure 3.67 conversion of ycbcr data into rgb format when the first-stage conversion circuit is selected by setting the rgb bit in vimr to 1, the ycbcr data sent from the video decoder is converted into rgb data for storage in the ugm. when the second-stage conversion circuit is selected by setting the vwry bit in dsmr2 to 1, the ycbcr data sent from the video decoder is converted into rgb data when the video screen is displayed. this makes it possible to store data in either the yuv or rgb for mat. when the first-stage circuit is applied to store rgb data in the ugm, the stored d ata can provide multi-valued source data for use in drawing. when the foreground or background screen is specified as being in the 16-bit/pixel mode, the rgb video data in a given screen area can be directly captured for display other than on the video screen. when the second-stage conversion circuit is used, the ycbcr data in the video capture area may be captured by the cpu for display elsewhere. 15 10 0 11 4 5 g (5 bits) b (5 bits) r (5 bits) figure 3.68 the rgb data format (16 bits/pixel) 3.7 video display function 3.7.1 video screen display setting the vwe bit of display mode register 2 ( dsmr2) places the data from the video-capture area (vsa0 to 2) ind icated by vid of the video-capture mode register (vimr) on the video screen in 16-bit/pixel mode. when the video-capture function is in operation, the area read for display as the current screen is automatically switched according to the specification in vid. the position at which the video screen is displayed is specified by the video display start position register. before the vwe bit is set to 1, the initial value should be set to the video display start position register. the display size is specified by the vsizex and vsizey bits. the data is displayed on an independent window (video screen). set a display position within the display area specified by dsx/dsy. the s ize of video screen is the same as that of a captured area. in the non-interlace display mode, the video image can be rev. 2.0, 09/02, page 129 of 366 displayed at any desired position. in interlace sync & video and interlace mode, the y position must be an even number (the lowest available setting is 0). the following conditions apply to the settings in the vpr: video horizontal-display start-position register ( hvpr) ? dsx ? vsizex video vertical-display start-position register ( vvpr) = dsy > vsizey 0 dsx 0 dsy the image must not be drawn beyond the range of the display. display area figure 3.69 position of the video image 3.7.2 relationship between the display mode and video-capture mode the q2sd is able to display images in any of three modes according to the setting of the scm10 bit of the display-mode register (dsmr): the respective modes produce a non-interlace display, interlace display, and interlace sync & video display. four video-capture modes are available, and the way in which the video data is captured in the ugm varies according to the mode of capture. select the appropriate display mode for the correct display of the captured video data. (1) display of data captured in non-interlace mode the non-interlace capture mode is used when the video decoder outputs in non-interlace mode. the display of video data is completed for every vc. capture in this mode is compatible with non-interlace mode. in an interlace sync display, one field is dropped out (missing of field occurs). in interlace sync & video mode, a frame may be composed of even and odd data in reverse order from that in the original frame of video data. rev. 2.0, 09/02, page 130 of 366 frame 1 frame 2 frame 3 frame 4 frame 5 frame 6 frame 7 frame 8 frame 1 frame 4 frame 7 frame 2 frame 5 frame 8 frame 3 frame 6 v0 v1 v2 v0 v1 v2 v0 fb0 fb1 fb0 fb1 fb0 fb1 fb0 fb1 bg frame 1 frame 2 frame 3 frame 4 frame 5 frame 6 frame 7 frame 1 frame 3 frame 5 frame 7 fb0 fb0 fb1 fb1 fb0 fb0 fb1 fb1 bg frame 2 frame 4 frame 6 fb0 fb0 fb1 fb1 fb0 fb0 fb1 bg fb0 fb1 fb0 fb1 fb0 fb1 fb0 fb1 bg fb0 fb1 fb0 fb1 fb0 fb1 fb0 bg frame 2 frame 1 even 3 frame 4 frame 5 frame 6 frame 7 frame 2 frame 1 even 3 frame 4 frame 5 frame 6 frame 7 non-interlace capture video decoder output video area 0 (v0) video area 1 (v1) video area 2 (v2) vid non-interlace mode display foreground screen (fg) background screen (bg) video screen (vw) interlace mode display (when odev = 0) foreground screen (fg) background screen (bg) video screen (vw) (when odev = 0) foreground screen (fg) background screen (bg) video screen (vw) interlace sync & video mode display (when odev = 0) foreground screen (fg) background screen (bg) video screen (vw) (when odev = 0) foreground screen (fg) background screen (bg) video screen (vw) high or low different frame composed figure 3.70 the display of data captured in interlace mode and display (2) display of data captured in interlace composite mode interlace composite mode is used when the video decoder outputs in interlace 2 format. in this capture mode, a frame of video data is displayed every 2 vc, and the data is composed at the ugm area. capture in this mode is comp atible with non-interlace and interlace mode. however, in interlace sync & video display mode, a frame may be incorrectly composed (e.g., the odd data for v0 is combined with the even data of v1) if the start of the capture operation does not match the start of the frame. if synchronization of the display of data with the timing of the data being captured is left to chance, there will be a 50% probability of the incorrect composition of the displayed frames. rev. 2.0, 09/02, page 131 of 366 even 1 odd 1 even 2 odd 2 even 3 odd 3 even 4 odd 4 even 1 odd 1 even 4 odd 4 even 2 odd 2 even 3 odd 3 v0 v1 v2 fb0 fb1 fb0 fb1 fb0 fb1 fb0 fb1 bg frame 1 frame 1 frame 2 frame 2 frame 3 frame 3 frame 1 frame 2 frame 3 odd 1 even 1 odd 2 even 2 odd 3 even 3 fb0 fb0 fb1 fb1 fb0 fb0 fb1 fb1 bg frame 1 frame 2 frame 3 fb0 fb0 fb1 fb1 fb0 fb0 fb1 bg fb0 fb1 fb0 fb1 fb0 fb1 fb0 fb1 bg fb0 fb1 fb0 fb1 fb0 fb1 fb0 bg odd 1 even 1 odd 2 even 2 odd 3 even 3 interlace composite capture video decoder output (vinm = 1) video area 0 (v0) video area 1 (v1) video area 2 (v2) vid non-interlace mode display foreground screen (fg) background screen (bg) video screen (vw) interlace mode display (when odev = 0) foreground screen (fg) background screen (bg) video screen (vw) (when odev = 0) foreground screen (fg) background screen (bg) video screen (vw) interlace sync & video mode display (when odev = 0) foreground screen (fg) background screen (bg) video screen (vw) (when odev = 0) foreground screen (fg) background screen (bg) video screen (vw) different frame composed figure 3.71 the display of data captured in the interlace composite mode (3) display of data captured in interlace odd-only mode interlace odd-only mode is used when the video decoder output in interlace format. in this capture mode, only the odd-field video data is captured for display. this mode is compatible with the non-interlace and interlace modes. however, in the interlace sync & video display mode, a frame may be incorrectly composed (e.g., the odd d ata for v0 is combined with the even data of v1) if the start of the capture operation does not match the start of the frame. if synchronization of the display of data with the timing of the data being captured is left to chance, there will be a 50% probability of the incorrect composition of the displayed frames. rev. 2.0, 09/02, page 132 of 366 even 1 odd 1 even 2 odd 2 even 3 odd 3 even 4 odd 4 odd 1 odd 4 odd 2 odd 3 v0 v1 v2 fb0 fb1 fb0 fb1 fb0 fb1 fb0 fb1 bg odd 1 odd 1 odd 2 odd 2 odd 3 odd 3 odd 1 odd 2 odd 3 odd 1 odd 1 odd 2 odd 2 odd 3 odd 3 fb0 fb0 fb1 fb1 fb0 fb0 fb1 fb1 bg odd 1 odd 2 odd 3 fb0 fb0 fb1 fb1 fb0 fb0 fb1 bg fb0 fb1 fb0 fb1 fb0 fb1 fb0 fb1 bg fb0 fb1 fb0 fb1 fb0 fb1 fb0 bg odd 1 odd 1 odd 2 odd 2 odd 3 odd 3 interlace odd capture video decoder output video area 0 (v0) video area 1 (v1) video area 2 (v2) vid non-interlace mode display foreground screen (fg) background screen (bg) video screen (vw) interlace mode display (when odev = 0) foreground screen (fg) background screen (bg) video screen (vw) (when odev = 0) foreground screen (fg) background screen (bg) video screen (vw) interlace sync & video mode display (when odev = 0) foreground screen (fg) background screen (bg) video screen (vw) (when odev = 0) foreground screen (fg) background screen (bg) video screen (vw) different frame composed figure 3.72 the display of data captured in the interlace odd-only mode (4) display of data captured in interlace even-only mode interlace even-only mode is used when the video decoder output in interlace format. in this capture mode, display of video data is completed only by the data of the even field. this mode is compatible with the non-interlace and interlace mode. however, in the interlace sync & video display mode, a frame may be incorrectly composed (e.g., the odd d ata for v0 is combined with the even data of v1) if the start of the capture operation does not match the start of the frame. if synchronization of the display of data with the timing of the data being captured is left to chance, there will be a 50% probability of the incorrect composition of the displayed frames. rev. 2.0, 09/02, page 133 of 366 even 1 odd 1 even 2 odd 2 even 3 odd 3 even 4 odd 4 even 1 even 4 even 2 even3 v0 v0 v1 v2 fb0 fb1 fb0 fb1 fb0 fb1 fb0 fb1 bg even 1 even 1 even 2 even 2 even 3 even 3 even 1 even 2 even 3 even 4 even 1 even 1 even 2 even 2 even 3 even 3 even 4 fb0 fb0 fb1 fb1 fb0 fb0 fb1 fb1 bg even 1 even 2 even 3 fb0 fb0 fb1 fb1 fb0 fb0 fb1 bg even 4 fb0 fb1 fb0 fb1 fb0 fb1 fb0 fb1 bg fb0 fb1 fb0 fb1 fb0 fb1 fb0 bg even 1 even 4 even 1 even 2 even 2 even 3 even 3 interlace even capture video decoder output video area 0 (v0) video area 1 (v1) video area 2 (v2) vid non-interlace mode display foreground screen (fg) background screen (bg) video screen (vw) interlace mode display (when odev = 0) foreground screen (fg) background screen (bg) video screen (vw) (when odev = 0) foreground screen (fg) background screen (bg) video screen (vw) interlace sync & video mode display (when odev = 0) foreground screen (fg) background screen (bg) video screen (vw) (when odev = 0) foreground screen (fg) background screen (bg) video screen (vw) different frame composed figure 3.73 the display of data captured in the interlace even-only mode (5) selecting the display mode the result of analysis of compatibility between the video capture mode and q2sd display mode are given in table 3.13. the entries a in the table indicate combinations that are recommended without reservation. the entries b in the table indicate that a sufficient resolution may be obtained by setting the output of the video decoder to non-interlace mode. however, if this mode is used in interlace mode, the vertical size of the captured image is ? that of the original (i.e., the resolution of the image is halved). rev. 2.0, 09/02, page 134 of 366 the entries c in the table indicate that the smoothness of the sequence of images will be disrupted (frames will be missing), or different frame composition (blurring or overlap when the shot changes frame to frame) occurs. table 3.12 selecting modes of video capture and display for the q2sd non-interlace display mode interlace sync display mode interlace sync & video display mode * 2 non- interlace capture b when the output of the video decoder is set to interlace sync mode, pay attention to the display size (the display size is reduced to 1/2 that of the source size). c missing frame occurs. when the output of the video decoder is set to interlace sync mode, pay attention to the display size (the display size is reduced to 1/2 that of the source size). d different frames are composed. when the output of the video decoder is set to interlace sync mode, pay attention to the display size (the display size is reduced to 1/2 that of the source size). interlace composite capture a no problem (the display is the same as with interlace mode) a no problem c different frames are composed. interlace odd capture b when the output of the video decoder is set to interlace sync mode, pay attention to the display size (the display size is reduced to 1/2 that of the source size). * 1 b when the output of the video decoder is set to interlace sync mode, pay attention to the display size (the display size is reduced to 1/2 that of the source size). * 1 c different frames are composed. when the output of the video decoder is set to interlace sync mode, pay attention to the display size (the display size is reduced to 1/2 that of the source size). interlace even capture b when the output of the video decoder is set to interlace sync mode, pay attention to the display size (the display size is reduced to 1/2 that of the source size). * 1 b when the output of the video decoder is set to interlace sync mode, pay attention to the display size (the display size is reduced to 1/2 that of the source size). * 1 c different frames are composed. when the output of the video decoder is set to interlace sync mode, pay attention to the display size (the display size is reduced to 1/2 that of the source size). rev. 2.0, 09/02, page 135 of 366 notes: 1. when the video decoder is placed in the non-interlace mode, the corresponding mode cannot be used if the field signal is output. 2. the frame is changed field by field (1/60 sec) in q2sd interlace sync & video display mode since the vid of the video screen is checked for each field. the data which belongs to a single screen when captured is not divided into odd and even fields when displayed. after only a half of captured data has been displayed, the next captured data starts to be displayed. therefore, the data in the y direction are halved when the data is captured in interlace, interlace odd-only, or interlace even-only mode in which a frame consists of two-field. if the data captured in this way is displayed on a monitor in non-interlace mode, the screen is halved in the y direction, and if the data captured is displayed on a tv in interlace mode, the screen on which an even field and an odd field for different frames are composed is displayed. when the video data for one frame is captured over 1/30 s in the interlaced-composite capture mode but the first field to be captured is the second in the pair of fields, the timing of the captured data will be incorrect when it is displayed. this may lead to the composite display of data for different frames. to avoid this, enter the external synchronization mode and the video capture signals (the vertical sync input (vvs), horizontal sync input (vhs), and field (vodd) signals) are input to the exvsync, exhsync, and oddf pins for synchronization. rev. 2.0, 09/02, page 136 of 366 rev. 2.0, 09/02, page 137 of 366 section 4 display list table 4.1 command list type command name function polygon4a performs any four-vertex drawing at rendering coordinates while referencing a multi-valued (8- or 16-bit/pixel) source. four-vertex screen drawing polygon4b performs any four-vertex drawing at rendering coordinates while referencing a binary (1-bit/pixel) source. polygon4c performs any four-vertex drawing at rendering coordinates with a monochrome specification. line drawing line draws a solid line 1 to 5 bits in width at rendering coordinates. rline draws a solid line 1 to 5 bits in width at rendering coordinates. pline draws a polygonal line at rendering coordinates while referencing a binary source. rpline draws a polygonal line at rendering coordinates while referencing a binary source. ftrap draws a polygon at work coordinates. work screen drawing command rftrap draws a polygon at work coordinates. clrw zeroizes the work coordinates. work line drawing linew draws a 1-bit-wide solid line at work coordinates. rlinew draws a 1-bit-wide solid line at work coordinates. move sets the current pointer. register setting commands rmove sets the current pointer. lcofs sets the local offset. rlcofs sets the local offset. sclip sets the system clipping area. uclip sets the user clipping area. wpr sets a value in a specific address-mapped register. jump changes the display list fetch destination. sequence control commands gosub makes a subroutine call for the display list. ret returns from a subroutine call made by the gosub command. nop3 executes no operation. vbkem performs synchronization with the frame c hange timing. trap informs the q2sd of the end of the display list. rev. 2.0, 09/02, page 138 of 366 4.1 four-vertex screen drawing 4.1.1 polygon4a function performs any four-vertex drawing at rendering coordinates while referencing a multi-valued (8- or 16-bit/pixel) source. command format lni = 0 15 draw mode code 0 dy4 dx4 dy3 dx3 dy2 dx2 dy1 dx1 sign extension tdy tdx tys txs sign sign extension sign sign extension sign sign extension sign sign extension sign sign extension sign sign extension sign sign extension sign rev. 2.0, 09/02, page 139 of 366 lni = 1, rel = 0 15 draw mode code 0 dy4 dx4 dy3 dx3 dy2 dx2 dy1 dx1 sign extension tdy tdx absolute source address l absolute source address h sign sign extension sign sign extension sign sign extension sign sign extension sign sign extension sign sign extension sign sign extension sign lni = 1, rel = 1 15 draw mode code 0 dy4 dx4 dy3 dx3 dy2 dx2 dy1 dx1 tdy tdx relative source address l relative source address h sign sign sign extension sign sign extension sign sign extension sign sign extension sign sign extension sign sign extension sign sign extension sign sign extension sign extension rev. 2.0, 09/02, page 140 of 366 1. code b'00000 2. rendering attributes reference data drawing destination multi-valued source binary source binary work specified color rendering work oao draw mode reserved trns styl clip rel net eos fst lni coof work fixed at 0 ** oz ** o * o * o: can be used v: can be used (specified color is binary eos bit value) a: referenced depending on mode (valid when work = 1) * : referenced depending on mode (clear to 0 when fst = 1) z: referenced depending on mode (clear to 0 when lni = 1) blank: cannot be used (clear to 0) 3. command parameters txs, tys: source starting point absolute/relative source address h: source start upper address (byte address) absolute/relative source address l: source start lower address (byte address) tdx, tdy: source size dxn, dyn (n = 1 to 4): absolute values, rendering coordinates, negative numbers expressed as two's complement rev. 2.0, 09/02, page 141 of 366 description transfers multi-valued (8- or 16-bit/pixel) source data to any quadrilateral rendering coordinates. the source is always scanned horizontally, but diagonal scanning may be used in the drawing, depending on the shape. in diagonally-scanned drawing, double-writing occurs to fill in gaps. when lni = 1, set a multiple of 8 pixels as the tdx value. when lni = 0, set 8 pixels or more as the tdx value. if the tdx setting is less than 8 pixels, multi-valued source references will not be performed normally. 1. when repeated source referencing is selected as a rendering attribute (styl = 1), the source is not enlarged or reduced, but is referenced repeatedly. 2. when work referencing is selected as a rendering attribute (work = 1), only places where the work coordinate pixel is 1 are drawn at rendering coordinates while referencing work coordinates for the same coordinates as the rendering coordinates. 3. when lni = 0, make txs and tys settings in pixel units. 4. when lni = 1, the linear address space in the ugm can be used for mu lti-valued source coordinates. see section 3.3.3 (4) multi-valued source coordinates. when lni = 1, set the upper bits of the source address in source address h, and the lower bits in source address l. when rel = 0, the source address can be sp ecified as an absolute address. when rel = 1, the source address can be specified as a relative address with respect to the ugm address at which the polygon4a co mmand code is located. absolute addresses and relative addresses must be even numbers. if a relative address is negative, its two's complement should be used. in 16-bit/pixel drawing, if the rendering attribute c oof bit is set to 1, the result of adding the value in the color register to the value of the multi-valued source data is drawn. the operation is performed by saturation processing. in 8-bit/pixel drawing, the c oof bit must be cleared to 0. note on fst mode when the register attribute fst bit is set to 1, processing is carried out in 4-pixel units. however, operation will be executed normally only if all the following conditions are satisfied; in other cases, operation cannot be guaranteed. evaluation of these conditions is not performed internally. make settings so that the source and destination are rectangles of the same size, with dx1 = dx4 = 4j C 4, dx2 = dx3 = 4k C 1, dy1 = dy2, dy3 = dy4, dx2 C dx1 = 32n C 1 (where j, k, and n are natural numbers). when fst = 1, no other rendering attributes except clip can be used. rev. 2.0, 09/02, page 142 of 366 when this command is used with fst = 1, first use the move, rmove, lcofs, or rlcofs co mmand to change the clipping range and local offset values to the values given in the descriptions of the individual commands. set a multiple of 4 for txs and tys. operation is valid in 8-bit/pixel and 16-bit/pixel modes. the local offset values set by the lc ofs and rlcofs co mmands must be non-negative. example rendering coordinates (dx1, dy1) (dx4, dy4) (dx2, dy2) (dx3, dy3) no work specification (work = 0) work specification provided (work = 1) (dx1, dy1) (dx4, dy4) rendering coordinates (dx2, dy2) (dx3, dy3) tdx tdy (txs, tys) multi-valued source coordinates (dx1, dy1) (dx4, dy4) work coordinates (dx2, dy2) (dx3, dy3) rev. 2.0, 09/02, page 143 of 366 4.1.2 polygon4b function performs any four-vertex drawing at rendering coordinates while referencing a binary (1-bit/pixel) source. command format rel = 0 draw mode code 15 0 color 1 color 0 dy4 dx4 dy3 dx3 dy2 dx2 dy1 dx1 tdy tdx absolute source address l absolute source address h : fixed at 0 sign extension sign sign extension sign sign extension sign sign extension sign sign extension sign sign extension sign sign extension sign sign extension sign rev. 2.0, 09/02, page 144 of 366 rel = 1 draw mode code 15 0 color 1 color 0 dy4 dx4 dy3 dx3 dy2 dx2 dy1 dx1 tdy tdx : fixed at 0 sign extension sign sign extension sign sign extension sign sign extension sign sign extension sign sign extension sign sign extension sign sign extension sign relative source address l relative source address h sign sign extension rev. 2.0, 09/02, page 145 of 366 1. code b'00001 2. rendering attributes reference data drawing destination multi-valued source binary source binary work specified color rendering work oa o draw mode reserved trns styl clip rel net eos reserved reserved half work fixed at 0 oo*oooofixed at 0 fixed at 0 o* o o: can be used v: can be used (specified color is binary eos bit value) a: referenced depending on mode (valid when work = 1) * : referenced depending on mode (clear to 0 when fst = 1) z: referenced depending on mode (clear to 0 when lni = 1) blank: cannot be used (clear to 0) note: * the styl bit and half bit cannot both be set to 1 at the same time. 3. command parameters absolute/relative source address h: 1-b it/pixel source start upper address (byte address) absolute/relative source address l: 1-b it/pixel source start lower address (byte address) tdx, tdy: source size dxn, dyn (n = 1 to 4): absolute values, rendering coordinates, negative numbers expressed as two's complement color0, color1: 8- or 16-bit/pixel color specifications rev. 2.0, 09/02, page 146 of 366 description draws binary (1-bit/pixel) source data in any quadrilateral rendering area, using the colors specified by parameters color0 and color1. for the color0 and color1 data formats, see section 3.2.9, input color data configuration. the source is always scanned horizontally, but diagonal scanning may be used in the drawing, depending on the shape. in diagonally- scanned drawing, double-writing occurs to fill in gaps. a multiple of 8 pixels must be set as the tdx value. 1. when repeated source referencing is selected as a rendering attribute (styl = 1), the source is not enlarged or reduced, but is referenced repeatedly. 2. when work referencing is selected as a rendering attribute (work = 1), only places where the work coordinate pixel is 1 are drawn at rendering coordinates while referencing work coordinates for the same coordinates as the rendering coordinates. binary source data is located in an area in the ugm. when rel = 0, the source address can be specified as an absolute address. when rel = 1, the source address can be specified as a relative address with respect to the ugm address at which the polygon4b co mmand code is located. absolute addresses and relative addresses must be even numbers. if a relative address is negative, its two's complement should be used. example tdx tdy source address binary source coordinates binary source 0 data is transparent. transparent mode (trns = 1) non-transparent mode (trns = 0) color 0 color 1 color 1 (dx1, dy1) (dx4, dy4) rendering coordinates (dx2, dy2) (dx3, dy3) (dx1, dy1) (dx4, dy4) rendering coordinates (dx2, dy2) (dx3, dy3) rev. 2.0, 09/02, page 147 of 366 4.1.3 polygon4c function performs any four-vertex drawing at rendering coordinates with a monochrome specification. command format draw mode code 15 0 color dy4 dx4 dy3 dx3 dy2 dx2 dy1 dx1 sign extension sign sign extension sign sign extension sign sign extension sign sign extension sign sign extension sign sign extension sign sign extension sign rev. 2.0, 09/02, page 148 of 366 1. code b'00010 2. rendering attributes reference data drawing destination multi-valued source binary source binary work specified color rendering work aoo draw mode reserved clip reserved net eos fst reserved work fixed at 0 fixed at 0 fixed at 0 ofixed at 0 ** ofixed at 0 fixed at 0 * o: can be used v: can be used (specified color is binary eos bit value) a: referenced depending on mode (valid when work = 1) * : referenced depending on mode (clear to 0 when fst = 1) z: referenced depending on mode (clear to 0 when lni = 1) blank: cannot be used (clear to 0) 3. command parameters dxn, dyn (n = 1 to 4): absolute values, rendering coordinates, negative numbers expressed as two's complement color: 8- or 16-bit/pixel color specification rev. 2.0, 09/02, page 149 of 366 description draws any quadrilateral in the rendering area in the single color specified by the color parameter. for the color data format, see section 3.2.9, input color data format configuration. when work referencing is selected as a rendering attribute (work = 1), only places where the work coordinate pixel is 1 are drawn at rendering coordinates while referencing work coordinates for the same coordinates as the rendering coordinates. when the register attribute fst bit is set to 1, processing is carried out in 4-pixel units. however, operation will be executed normally only if all the following conditions are satisfied; in other cases, operation cannot be guaranteed. evaluation of these conditions is not performed internally. make settings so that the source and destination are rectangles of the same size, with dx1 = dx4 = 4j C 4, dx2 = dx3 = 4k C 1, dy1 = dy2, dy3 = dy4, dx2 C dx1 = 32n C 1 (where j, k, and n are natural numbers). when fst = 1, no other rendering attributes except clip can be used. when this command is used with fst = 1, first use the move, rmove, lcofs, or rlcofs co mmand to change the clipping range and local offset values to the values given in the descriptions of the individual commands. operation is valid in 8-bit/pixel and 16-bit/pixel modes. in 8-bit/pixel mode, set the same 8- bit data for the upper and lower color attribute values. the local offset values set by the lc ofs and rlcofs co mmands must be non-negative. rev. 2.0, 09/02, page 150 of 366 example color work specification no work specification (dx1, dy1) (dx2, dy2) (dx3, dy3) (dx4, dy4) (dx1, dy1) (dx2, dy2) (dx3, dy3) (dx4, dy4) (dx1, dy1) (dx2, dy2) (dx3, dy3) (dx4, dy4) work coordinates rendering coordinates rendering coordinates color specified color specified color rev. 2.0, 09/02, page 151 of 366 4.2 line drawing 4.2.1 line function draws a solid line 1 to 5 bits in width at rendering coordinates. command format 15 0 line color dyn dxn dy2 dx2 dy1 dx1 n . . . draw mode code sign extension sign sign extension sign sign extension sign sign extension sign sign extension sign sign extension sign 1. code b'01100 2. rendering attributes reference data drawing destination multi-valued source binary source binary work specified color rendering work oo rev. 2.0, 09/02, page 152 of 366 draw mode reserved clip reserved net eos fwul w2ul fwdr w2dr fixed at 0 fixed at 0 fixed at 0 ofixed at 0 o o 0000 to 1111 o: can be used v: can be used (specified color is binary eos bit value) a: referenced depending on mode (valid when work = 1) * : referenced depending on mode (clear to 0 when fst = 1) z: referenced depending on mode (clear to 0 when lni = 1) blank: cannot be used (clear to 0) 3. command parameters line color: 8- or 16-bit/pixel color specification n (n = 2 to 65,535): number of vertices dxn (n = 2 to 65,535): absolute values, rendering coordinates, negative numbers expressed as two's complement dyn (n = 2 to 65,535): absolute values, rendering coordinates, negative numbers expressed as two's complement description draws a polygonal line at rendering coordinates from vertex 1 (dx1, dy1), through vertex 2 (dx2, dy2), ...., vertex n C 1 (dxn C 1, dyn C 1), to vertex n (dxn, dyn), using the single color specified by parameter line color. for the line color data format, see section 3.2.9, input color data configuration. note: 8-point drawing is used. rev. 2.0, 09/02, page 153 of 366 example (dx2, dy2) (dx3, dy3) (dx1, dy1) (0, 0) n = 3 rendering coordinates rev. 2.0, 09/02, page 154 of 366 4.2.2 rline function draws a solid line 1 to 5 bits in width at rendering coordinates. command format 15 0 line color dx1 dy1 dx2 dy2 dxn dyn n . . . draw mode code sign sign sign sign sign sign 1. code b'01101 2. rendering attributes reference data drawing destination multi-valued source binary source binary work specified color rendering work oo draw mode reserved clip reserved net eos fwul w2ul fwdr w2dr fixed at 0 fixed at 0 fixed at 0 ofixed at 0 o o 0000 to 1111 o: can be used v: can be used (specified color is binary eos bit value) a: referenced depending on mode (valid when work = 1) * : referenced depending on mode (clear to 0 when fst = 1) z: referenced depending on mode (clear to 0 when lni = 1) blank: cannot be used (clear to 0) 3. command parameters line color: 8- or 16-bit/pixel color specification rev. 2.0, 09/02, page 155 of 366 n (n = 1 to 65,535): number of vertices dxn, dyn (n = 1 to 65,535): relative values, rendering coordinates, negative numbers expressed as two's complement description draws, at rendering coordinates, a polygonal line comprising line segments (xc, yc) C (xc + dx1, yc + dy1), (xc + dx1, yc + dy1) C (xc + dx1 + dx2, yc + dy1 + dy2), ..., (xc + ... + dxn C 1, yc + ... + dyn C 1) C (xc + ... + dxn C 1 + dxn, yc + ... + dyn C 1 + dyn) to the coordinates specified by the relative shift (dx, dy) from the current pointer values (xc, yc), using the single color specified by parameter line color. for the line color data format, see section 3.2.9, input color data format configuration. the final coordinate point is stored as the current pointer values (xc, yc). note: 8-point drawing is used. example (xc + dx1, yc + dy1) (0, 0) n = 2 rendering coordinates (xc, yc) dy2 dy1 dx1 dx2 (xc + dx1 + dx2, yc + dy1 + dy2) rev. 2.0, 09/02, page 156 of 366 4.2.3 pline function draws a polygonal line at rendering coordinates while referencing a binary source. command format dyn dxn dy2 dx2 dy1 dx1 n tdx lppt source address l source address h 15 0 line color 1 line color 0 . . . draw mode code : fixed at 0 sign extension sign sign extension sign sign extension sign sign extension sign sign extension sign sign extension sign rev. 2.0, 09/02, page 157 of 366 1. code b'01110 2. rendering attributes reference data drawing destination multi-valued source binary source binary work specified color rendering work oo draw mode reserved trns reserved clip reserved net eos edg2 reserved edg1 reserved fixed at 0 ofixed at 1 ofixed at 0 ooofixed at 0 ofixed at 1 o: can be used v: can be used (specified color is binary eos bit value) a: referenced depending on mode (valid when work = 1) * : referenced depending on mode (clear to 0 when fst = 1) z: referenced depending on mode (clear to 0 when lni = 1) blank: cannot be used (clear to 0) 3. command parameters line color0: 8- or 16-bit/pixel color specification line color1: 8- or 16-bit/pixel color specification source address h: 1-b it/pixel source start upper address (byte address) source address l: 1-b it/pixel source start lower address (byte address) tdx: source size lppt: line pattern pointer n (n = 2 to 65,535): number of vertices dxn (n = 2 to 65,535): absolute values, rendering coordinates, negative numbers expressed as two's complement dyn (n = 2 to 65,535): absolute values, rendering coordinates, negative numbers expressed as two's complement rev. 2.0, 09/02, page 158 of 366 description draws a polygonal line from vertex 1 (dx1, dy1), through vertex 2 (dx2, dy2), ...., vertex n C 1 (dxn C 1, dyn C 1), to vertex n (dxn, dyn). a multiple of 8 pixels must be set for the tdx value. the reference start position of the binary source data can be adjusted by setting a value between 0 and 7 in the line pattern pointer. for example, if 0 is set, referencing starts at the beginning of the source data, while if 5 is set, referencing starts 5 pixels from the beginning of the source data. when styl = 1, pattern repetition starts at the pixel after [source start position + tdx + lppt C 1]. the source start address must be an even number. note: 4-point drawing is used. example source address trns = 1 and styl = 1 specified (dx2, dy2) (dx3, dy3) (dx1, dy1) (0, 0) n = 3 rendering coordinates tdx 1100 1100 1100 1100 l s b m s b rev. 2.0, 09/02, page 159 of 366 4.2.4 rpline function draws a polygonal line at rendering coordinates while referencing a binary source. command format source address l source address h 15 0 line color 1 line color 0 draw mode code n tdx dx1 dy1 dx2 dy2 dxn dyn . . . : fixed at 0 lppt sign sign sign sign sign sign rev. 2.0, 09/02, page 160 of 366 1. code b'01111 2. rendering attributes reference data drawing destination multi-valued source binary source binary work specified color rendering work oo draw mode reserved trns reserved clip reserved net eos edg2 reserved edg1 reserved fixed at 0 ofixed at 1 ofixed at 0 ooofixed at 0 ofixed at 1 o: can be used v: can be used (specified color is binary eos bit value) a: referenced depending on mode (valid when work = 1) * : referenced depending on mode (clear to 0 when fst = 1) z: referenced depending on mode (clear to 0 when lni = 1) blank: cannot be used (clear to 0) 3. command parameters line color0: 8- or 16-bit/pixel color specification line color1: 8- or 16-bit/pixel color specification source address h: 1-b it/pixel source start upper address (byte address) source address l: 1-b it/pixel source start lower address (byte address) lppt: line pattern pointer tdx: source size n (n = 1 to 65,535): number of vertices dxn, dyn (n = 1 to 65,535): relative values, rendering coordinates, negative numbers expressed as two's complement rev. 2.0, 09/02, page 161 of 366 description draws a polygonal line comprising line segments (xc, yc) C (xc + dx1, yc + dy1), (xc + dx1, yc + dy1) C (xc + dx1 + dx2, yc + dy1 + dy2), ..., (xc + ... + dxn C 1, yc + ... + dyn C 1) C (xc + ... + dxn C1 + dxn, yc + ... + dyn C 1 + dyn) to the c oordinates specified by the relative shift (dx, dy) from the current pointer values (xc, yc). the final coordinate point is stored as the current pointer values (xc, yc). a multiple of 8 pixels must be set for the tdx value. the reference start position of the binary source data can be adjusted by setting a value between 0 and 7 in the line pattern pointer. for example, if 0 is set, referencing starts at the beginning of the source data, while if 5 is set, referencing starts 5 pixels from the beginning of the source data. when styl = 1, pattern repetition starts at the pixel after [source start position + tdx + lppt C 1]. the source start address must be an even number. note: 4-point drawing is used. example source address trns = 1 and styl = 1 specified tdx 1100 1100 1100 1100 l s b m s b (xc + dx1, yc + dy1) (0, 0) n = 2 rendering coordinates (xc, yc) dy2 dy1 dx1 dx2 (xc + dx1 + dx2, yc + dy1 + dy2) rev. 2.0, 09/02, page 162 of 366 4.3 work screen drawing command 4.3.1 ftrap function draws a polygon at work coordinates. command format 15 0 n dyn dxn dy2 dx2 dy1 dx1 dxl . . . draw mode code sign extension sign extension sign extension sign extension sign extension sign extension sign extension sign sign sign sign sign sign sign 1. code b'01000 2. rendering attributes reference data drawing destination multi-valued source binary source binary work specified color rendering work o rev. 2.0, 09/02, page 163 of 366 draw mode reserved clip reserved eos edg reserved fixed at 0 fixed at 0 fixed at 0 ofixed at 0 fixed at 0 b o fixed at 0 fixed at 0 fixed at 0 o: can be used v: can be used (specified color is binary eos bit value) a: referenced depending on mode (valid when work = 1) b: referenced depending on mode (valid when edg = 1) * : referenced depending on mode (clear to 0 when fst = 1) z: referenced depending on mode (clear to 0 when lni = 1) blank: cannot be used (clear to 0) 3. command parameters n (n = 2 to 65,535): number of vertices dxl: left-hand side coordinate dxn (n = 2 to 65,535): absolute value, work coordinate, negative number expressed as two's complement dyn (n = 2 to 65,535): absolute value, work coordinate, negative number expressed as two's complement description draws a polygon with n-1 vertices at work coordinates. paints n-1 trapezoids at work coordinates using binary eor, with x = dxl as the left-hand side, and line segments (dx1, dy1) C (dx2, dy2), (dx2, dy2) C (dx3, dy3), ..., (dx n-1, dyn-1) C (dxn, dyn) as the right-hand sides, and with top and bottom bases parallel to the x-axis. bottom base drawing is not performed. set the minimum value of dx1 to dxn as dxl. if the draw mode edg bit is set to 1, an edge line is drawn after the paint operation. the line drawing data is selected with the eos bit. when setting the edg bit to 1, set ( dxn, dyn) = (dx1, dy1) to give a closed figure. rev. 2.0, 09/02, page 164 of 366 example dxl painting order dxl dxl (dx1, dy1) (0, 0) n = 5 dxl work coordinates (dx2, dy2) (dx3, dy3) (dx4, dy4) dxl dxl order of listing ftrap parameters n dxl dx1 dy1 dx2 dy2 dx3 dy3 dx4 dy4 dx1 dy1 add the starting point at the end listing order rev. 2.0, 09/02, page 165 of 366 4.3.2 rftrap draws a polygon at work coordinates. command format 15 0 n dx1 dy1 dx2 dy2 dxn dyn dxl . . . draw mode code sign extension sign sign sign sign sign sign sign 1. code b'01001 2. rendering attributes reference data drawing destination multi-valued source binary source binary work specified color rendering work o draw mode reserved clip reserved eos edg reserved fixed at 0 fixed at 0 fixed at 0 ofixed at 0 fixed at 0 b o fixed at 0 fixed at 0 fixed at 0 o: can be used v: can be used (specified color is binary eos bit value) a: referenced depending on mode (valid when work = 1) b: referenced depending on mode (valid when edg = 1) * : referenced depending on mode (clear to 0 when fst = 1) z: referenced depending on mode (clear to 0 when lni = 1) blank: cannot be used (clear to 0) 3. command parameters n (n = 1 to 65,535): number of vertices rev. 2.0, 09/02, page 166 of 366 dxl: left-hand side coordinate, work coordinate, negative number expressed as two's complement dxn, dyn (n = 1 to 65,535): relative values, work coordinates, negative numbers expressed as two's complement description paints n trapezoids at work coordinates using binary eor, with x = dxl as the left-hand side, and line segments specified by the relative shift (dx, dy) from the current pointer values (xc, yc) ((xc, yc) C (xc + dx1, yc + dy1), (xc + dx1, yc + dy1) C (xc + dx1 + dx2, yc + dy1 + dy2), ..., (xc + ... + dxn C 1, yc + ... + dyn C 1) C (xc + ... + dxn C1 + dxn, yc + ... + dyn C 1 + dy n)) as the right-hand sides, and with top and bottom bases parallel to the x- axis. bottom base drawing is not performed. the final coordinate point is stored as the current pointer values (xc, yc). if the draw mode edg bit is set to 1, an edge line is drawn after the paint operation. the line drawing data is selected with the eos bit. when setting the edg bit to 1, set (dx1 + dx2 + ... + dxn = 0, dy1 + dy2 + ... + dyn = 0) to give a closed fi gure. rev. 2.0, 09/02, page 167 of 366 example dxl painting order dxl dxl (xc, yc) (0, 0) when n = 3 work coordinates dx3 dx2 dx1 dy1 dy2 (xc + dx1 + dx2 + dx3, yc + dy1+ dy2+ dy3) (xc + dx1, yc + dy1) dxl dxl (xc + dx1 + dx2, yc + dy1 + dy2) rev. 2.0, 09/02, page 168 of 366 4.3.3 clrw function zeroizes the work coordinates. command format 0 xmin ymin xmax ymax 15 draw mode code sign extension sign extension sign extension sign extension sign sign sign sign 1. code b'10100 2. rendering attributes reference data drawing destination multi-valued source binary source binary work specified color rendering work o draw mode reserved clip reserved fixed at 0 fixed at 0 fixed at 0 ofixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 o: can be used v: can be used (specified color is binary eos bit value) a: referenced depending on mode (valid when work = 1) *: referenced depending on mode (clear to 0 when fst = 1) z: referenced depending on mode (clear to 0 when lni = 1) blank: cannot be used (clear to 0) 3. command parameters xmin, xmax: left and right x coordin ate values, work coordinates, negative numbers expressed as two's complement ymin, ymax: upper and lower y coordin ate values, work coordinates, negative numbers expressed as two's complement rev. 2.0, 09/02, page 169 of 366 description zero-clears the area specified by upper-left coordinates (xmin, ymin) and lower-right coordinates ( xmax, ymax) in the work coordin ate system. example (0, 0) work coordinates (xmin, ymin) (xmax, ymax) rev. 2.0, 09/02, page 170 of 366 4.4 work line drawing 4.4.1 linew function draws a 1-bit-wide solid line at work coordinates. command format 0 15 n dyn dxn dy2 dx2 dy1 dx1 . . . draw mode code sign extension sign sign extension sign sign extension sign sign extension sign sign extension sign sign extension sign 1. code b'01010 2. rendering attributes reference data drawing destination multi-valued source binary source binary work specified color rendering work vo rev. 2.0, 09/02, page 171 of 366 draw mode reserved clip reserved eos reserved fixed at 0 fixed at 0 fixed at 0 ofixed at 0 fixed at 0 ofixed at 0 fixed at 0 fixed at 0 fixed at 0 o: can be used v: can be used (specified color is binary eos bit value) a: referenced depending on mode (valid when work = 1) * : referenced depending on mode (clear to 0 when fst = 1) z: referenced depending on mode (clear to 0 when lni = 1) blank: cannot be used (clear to 0) 3. command parameters n (n = 2 to 65,535): number of vertices dxn (n = 2 to 65,535): absolute value, work coordinate, negative number expressed as two's complement dyn (n = 2 to 65,535): absolute value, work coordinate, negative number expressed as two's complement description performs binary drawing at work coordinates of a polygonal line from vertex 1 (dx1, dy1), through vertex 2 (dx2, dy2), ...., vertex n C 1 (dxn C 1, dyn C 1), to vertex n (dxn, dyn). 0 drawing or 1 drawing is selected with the drawing mode eos bit. drawing is performed at work coordinates with 0 when eos = 0, and at work coordinates with 1 when eos = 1. (used for border drawing at work coordinates for a polygonal painted figure.) note: 8-point drawing is used. example rev. 2.0, 09/02, page 172 of 366 (dx2, dy2) (dx3, dy3) (dx1, dy1) (0, 0) n = 3 work coordinates rev. 2.0, 09/02, page 173 of 366 4.4.2 rlinew function draws a 1-bit-wide solid line at work coordinates. command format 15 0 n dx1 dy1 dx2 dy2 dxn dyn . . . draw mode code sign sign sign sign sign sign 1. code b'01011 2. rendering attributes reference data drawing destination multi-valued source binary source binary work specified color rendering work vo draw mode reserved clip reserved eos reserved fixed at 0 fixed at 0 fixed at 0 ofixed at 0 fixed at 0 ofixed at 0 fixed at 0 fixed at 0 fixed at 0 o: can be used v: can be used (specified color is binary eos bit value) a: referenced depending on mode (valid when work = 1) * : referenced depending on mode (clear to 0 when fst = 1) z: referenced depending on mode (clear to 0 when lni = 1) blank: cannot be used (clear to 0) 3. command parameters n (n = 1 to 65,535): number of vertices rev. 2.0, 09/02, page 174 of 366 dxn, dyn (n = 1 to 65,535): relative values, work coordinates, negative numbers expressed as two's complement description performs binary drawing at work coordinates of a polygonal line comprising line segments (xc, yc) C (xc + dx1, yc + dy1), (xc + dx1, yc + dy1) C (xc + dx1 + dx2, yc + dy1 + dy2), ..., (xc + ... + dxn C 1, yc + ... + dyn C 1) C (xc + ... + dxn C1 + dxn, yc + ... + dyn C 1 + dyn) to the coordinates specified by the relative shift (dx, dy) from the current pointer values (xc, yc). 0 drawing or 1 drawing is selected with the drawing mode eos bit. drawing is performed at work coordinates with 0 when eos = 0, and at work coordinates with 1 when eos = 1. the final coordinate point is stored as the current pointer values (xc, yc). (used for border drawing at work coordinates for a polygonal painted figure.) note: 8-point drawing is used. example (xc + dx1, yc + dy1) (0, 0) n = 2 work coordinates (xc, yc) dy2 dy1 dx1 dx2 (xc + dx1 + dx2, yc + dy1 + dy2) rev. 2.0, 09/02, page 175 of 366 4.5 register setting commands 4.5.1 move function sets the current pointer. command format 15 0 xc yc draw mode code sign extension sign sign extension sign 1. code b'10000 2. rendering attributes reference data drawing destination multi-valued source binary source binary work specified color rendering work draw mode reserved fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 o: can be used v: can be used (specified color is binary eos bit value) a: referenced depending on mode (valid when work = 1) * : referenced depending on mode (clear to 0 when fst = 1) z: referenced depending on mode (clear to 0 when lni = 1) blank: cannot be used (clear to 0) 3. command parameters xc: absolute value, rendering coordinate, work coordinate, negative number expressed as two's complement yc: absolute value, rendering coordinate, work coordinate, negative number expressed as two's complement rev. 2.0, 09/02, page 176 of 366 description sets the values obtained by adding the local offset values to xc and yc in the current pointers. xc and yc are set as absolute coordinates. the current pointers are used by relative drawing commands only. after issuing a move co mmand, use relative drawing commands in succession. if an absolute drawing command is used during this sequence, the current pointers will be used as registers for internal computation, and the current pointer values will be lost. a move co mmand must be therefore be issued before using relative drawing commands again. example (0, 0) work coordinates rendering coordinates (xc, yc) rev. 2.0, 09/02, page 177 of 366 4.5.2 rmove function sets the current pointer. command format 15 0 xc yc draw mode code sign sign 1. code b'10001 2. rendering attributes reference data drawing destination multi-valued source binary source binary work specified color rendering work draw mode reserved fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 o: can be used v: can be used (specified color is binary eos bit value) a: referenced depending on mode (valid when work = 1) * : referenced depending on mode (clear to 0 when fst = 1) z: referenced depending on mode (clear to 0 when lni = 1) blank: cannot be used (clear to 0) 3. command parameters xc, yc: relative values, rendering coordinates, work coordinates, negative numbers expressed as two's complement rev. 2.0, 09/02, page 178 of 366 description adds xc and yc to the current pointers. example (0, 0) old (xc, yc) (xc, yc) (old xc + xc, old yc + yc) rendering coordinates work coordinates rev. 2.0, 09/02, page 179 of 366 4.5.3 lcofs function sets the local offset. command format 15 0 xo yo draw mode code sign extension sign sign extension sign 1. code b'10010 2. rendering attributes reference data drawing destination multi-valued source binary source binary work specified color rendering work draw mode reserved fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 o: can be used v: can be used (specified color is binary eos bit value) a: referenced depending on mode (valid when work = 1) * : referenced depending on mode (clear to 0 when fst = 1) z: referenced depending on mode (clear to 0 when lni = 1) blank: cannot be used (clear to 0) 3. command parameters xo, yo: local offset value absolute specifications, rendering coordinates, work coordinates, negative numbers expressed as two's complement rev. 2.0, 09/02, page 180 of 366 description sets the local offset with absolute coordinates. after these settings are made, these offset values are added in all subsequent coordinate specifications. these settings must be made at the start of the display list (the initial values are undefined). to reflect the local offset values in the current pointers, issue a move co mmand after the lcofs co mmand. when using a command that employs the fst specification, a multiple of 4 must be set for the xo value. use non-negative values for both xo and yo. example (0, 0) work coordinates rendering coordinates (xo1, yo1) (xo1 + dx2, yo1 + dy2) (xo1 + dx1, yo1 + dy1) line rev. 2.0, 09/02, page 181 of 366 4.5.4 rlcofs function sets the local offset. command format 15 0 draw mode code xo yo sign sign 1. code b'10011 2. rendering attributes reference data drawing destination multi-valued source binary source binary work specified color rendering work draw mode reserved fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 o: can be used v: can be used (specified color is binary eos bit value) a: referenced depending on mode (valid when work = 1) * : referenced depending on mode (clear to 0 when fst = 1) z: referenced depending on mode (clear to 0 when lni = 1) blank: cannot be used (clear to 0) 3. command parameters xo, yo: local offset value relative specifications, rendering coordinates, work coordinates, negative numbers expressed as two's complement rev. 2.0, 09/02, page 182 of 366 description adds xo and yo to the local offset. after these settings are made, these offset values are added in all subsequent coordinate specifications. to reflect the local offset values in the current pointers, issue a move co mmand after setting the local offset with the lc ofs or rlcofs co mmand. when using a command that employs the fst specification, the value obtained by adding xo to the local offset must be a multiple of 4. the local offset values set by xo and yo must be non-negative. example (0, 0) work coordinates rendering coordinates (old xo, old yo) (old xo + xo + dx1, old yo + yo + dy1) line xo yo (old xo + xo, old yo + yo) (old xo + xo + dx2, old yo + yo + dy2) rev. 2.0, 09/02, page 183 of 366 4.5.5 sclip function sets the system clipping area. command format xmax ymax 15 0 draw mode code : fixed at 0 1. code b'10111 2. rendering attributes reference data drawing destination multi-valued source binary source binary work specified color rendering work draw mode reserved fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 o: can be used v: can be used (specified color is binary eos bit value) a: referenced depending on mode (valid when work = 1) * : referenced depending on mode (clear to 0 when fst = 1) z: referenced depending on mode (clear to 0 when lni = 1) blank: cannot be used (clear to 0) 3. command parameters xmax: left and right x coordin ate values, rendering coordinates, work coordinates ymax: upper and lower y coordin ate values, rendering coordinates, work coordinates rev. 2.0, 09/02, page 184 of 366 description designates the area specified by upper-left coordinates (0, 0) and lower-right coordinates (xmax, ymax) in the rendering coordin ate and work coordinate systems as the system clipping area. the local offset values specified by the lc ofs or rlcofs co mmand are not added to the coordinates set by this command. set the maximum drawing range values for xmax and ymax. after powering on, the in itial values of the clipping range are undefined. the clipping range must therefore be set with the sclip command at the start of the first display list executed. for the set values given by this command, screen coordinates must be set as reference coordinates. when using a command that employs the fst specification, set a multiple of 4 C 1 as the xmax value. example (0, 0) work coordinates rendering coordinates (xmax, ymax) rev. 2.0, 09/02, page 185 of 366 4.5.6 uclip function sets the user clipping area. command format xmin ymin xmax ymax 15 0 draw mode code : fixed at 0 1. code b'10101 2. rendering attributes reference data drawing destination multi-valued source binary source binary work specified color rendering work draw mode reserved fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 o: can be used v: can be used (specified color is binary eos bit value) a: referenced depending on mode (valid when work = 1) * : referenced depending on mode (clear to 0 when fst = 1) z: referenced depending on mode (clear to 0 when lni = 1) blank: cannot be used (clear to 0) 3. command parameters xmin, xmax: left and right x coordin ate values, rendering coordinates, work coordinates rev. 2.0, 09/02, page 186 of 366 ymin, ymax: upper and lower y coordin ate values, rendering coordinates, work coordinates description designates the area specified by upper-left coordinates (xmin, ymin) and lower-right coordinates ( xmax, ymax) in the rendering coordin ate and work coordinate systems as a user clipping area. the local offset values specified by the lc ofs or rlcofs co mmand are not added to the coordinates set by this command. when making these settings, ensure that xmin < xmax and ymin < ymax, and that the system clipping area is not exceeded. this setting is valid when clip = 1. when using a command that employs the fst specification, set a multiple of 4 as the xmin value, and a multiple of 4 C 1 as the xmax value. example (0, 0) work coordinates rendering coordinates (xmin, ymin) (xmax, ymax) rev. 2.0, 09/02, page 187 of 366 4.5.7 wpr function sets a value in a specific address-mapped register. command format 15 15 10 draw mode code 0 rn data : fixed at 0 1. code b'10110 2. rendering attributes reference data drawing destination multi-valued source binary source binary work specified color rendering work draw mode reserved fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 o: can be used v: can be used (specified color is binary eos bit value) a: referenced depending on mode (valid when work = 1) * : referenced depending on mode (clear to 0 when fst = 1) z: referenced depending on mode (clear to 0 when lni = 1) blank: cannot be used (clear to 0) 3. command parameters rn: register number data: data rev. 2.0, 09/02, page 188 of 366 description writes data to the q2sd's address-mapped registers. the register number is set in rn, and the write data in data. when a write is performed to an address-mapped register with this command, select the location to ensure that the currently executing drawing processing is not adversely affected. also ensure that there is no conflict with access by the superh. this command is intended primarily for performing the operations shown in (a) to (e). (a) change of display start address or drawing start address (rn = 00a, 00b, 04c) (b) change of multi-valued source or work start address (rn = 00e, 00f) (c) change of graphic bit mode (rn = 006) (d) return address setting when performing resumption processing after drawing suspension (rn = 04a, 04b) (e) change of drawing color offset value when performing drawing processing (rn = 04d) the registers that can be written to are limited to those listed below. if a write is performed to another register, subsequent operation cannot be guaranteed. register no. register address name 00a: h 014 dsa0 00b: h 016 dsa1 00e: h 01c ssar 00f: h 01e wsar 04c: h 098 rsar 006: h 00c remr 04a: h 094 rtnh 04b: h 096 rtnl 04d: h 09a color rev. 2.0, 09/02, page 189 of 366 4.6 sequence control commands 4.6.1 jump function changes the display list fetch destination. command format rel = 0 15 draw mode code 0 absolute jump address l absolute jump address h : fixed at 0 rel = 1 15 draw mode code 0 : fixed at 0 relative jump address l relative jump address h sign sign extension 1. code b'11000 2. rendering attributes reference data drawing destination multi-valued source binary source binary work specified color rendering work rev. 2.0, 09/02, page 190 of 366 draw mode reserved rel reserved fixed at 0 fixed at 0 fixed at 0 fixed at 0 ofixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 o: can be used v: can be used (specified color is binary eos bit value) a: referenced depending on mode (valid when work = 1) * : referenced depending on mode (clear to 0 when fst = 1) z: referenced depending on mode (clear to 0 when lni = 1) blank: cannot be used (clear to 0) 3. command parameters absolute/relative jump address h: absolu te/relative jump destination upper address (byte address) absolute/relative jump address l: absolu te/relative jump destination lower address (byte address) description changes the display list fetch destination to the specified address. when rel = 0, the jump destination address can be specified as an absolute address. when rel = 1, the source address can be specified as a relative address with respect to the ugm address at which the command code is located. absolute addresses and relative addresses must be even numbers. if a relative address is negative, its two's complement should be used. example display list area drawing starts drawing command drawing command register setting command drawing command jump command . . rev. 2.0, 09/02, page 191 of 366 4.6.2 gosub function makes a subroutine call for the display list. command format rel = 0 15 draw mode code 0 absolute subroutine address l absolute subroutine address h : fixed at 0 rel = 1 15 draw mode code 0 : fixed at 0 relative subroutine address l relative subroutine address h sign sign extension 1. code b'11001 2. rendering attributes reference data drawing destination multi-valued source binary source binary work specified color rendering work rev. 2.0, 09/02, page 192 of 366 draw mode reserved rel reserved fixed at 0 fixed at 0 fixed at 0 fixed at 0 ofixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 o: can be used v: can be used (specified color is binary eos bit value) a: referenced depending on mode (valid when work = 1) * : referenced depending on mode (clear to 0 when fst = 1) z: referenced depending on mode (clear to 0 when lni = 1) blank: cannot be used (clear to 0) 3. command parameters absolute/relative subroutine address h: absolu te/relative subroutine upper address (byte address) absolute/relative subroutine address l: absolu te/relative subroutine lower address (byte address) description changes the display list fetch destination to the specified subroutine address. the fetch address is restored by an ret instruction. as only one level of nesting is permitted, it will not be possible to return if a subroutine call is issued within the subroutine. when rel = 0, the subroutine destination address can be specified as an absolute address. when rel = 1, the address can be specified as a relative address with respect to the ugm address at which the command code is located. absolute addresses and relative addresses must be even numbers. if a relative address is negative, its two's complement should be used. rev. 2.0, 09/02, page 193 of 366 example display list area subroutine drawing starts drawing command drawing command ret command register setting command drawing command drawing command gosub command . . rev. 2.0, 09/02, page 194 of 366 4.6.3 ret function returns from a subroutine call made by the gosub co mmand. command format 15 draw mode code 0 1. code b'11011 2. rendering attributes reference data drawing destination multi-valued source binary source binary work specified color rendering work draw mode reserved fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 o: can be used v: can be used (specified color is binary eos bit value) a: referenced depending on mode (valid when work = 1) * : referenced depending on mode (clear to 0 when fst = 1) z: referenced depending on mode (clear to 0 when lni = 1) blank: cannot be used (clear to 0) description restores the display list fetch destination to the address following the source of the subroutine call. rev. 2.0, 09/02, page 195 of 366 4.6.4 nop3 function executes no operation. command format 15 draw mode code 0 dummy dummy 1. code b'11110 2. rendering attributes reference data drawing destination multi-valued source binary source binary work specified color rendering work draw mode reserved fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 o: can be used v: can be used (specified color is binary eos bit value) a: referenced depending on mode (valid when work = 1) * : referenced depending on mode (clear to 0 when fst = 1) z: referenced depending on mode (clear to 0 when lni = 1) blank: cannot be used (clear to 0) description the nop3 co mmand does not perform any operation. this command, which consists of three words including the command code, simply fetches the next instruction without executing any processing. rev. 2.0, 09/02, page 196 of 366 4.6.5 vbkem function performs synchronization with the frame change timing. command format 15 draw mode code 0 dummy dummy 1. code b'11010 2. rendering attributes reference data drawing destination multi-valued source binary source binary work specified color rendering work draw mode reserved fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 o: can be used v: can be used (specified color is binary eos bit value) a: referenced depending on mode (valid when work = 1) * : referenced depending on mode (clear to 0 when fst = 1) z: referenced depending on mode (clear to 0 when lni = 1) blank: cannot be used (clear to 0) description when this command is executed, the drawing operation is kept waiting until the timing for a frame change. as soon as the frame change timing has elapsed, control passes to the next command. the frame change timing is every vbk in non-interlace and interlace & video modes, and every frm in interlace mode. do not use this command in auto display charge mode. rev. 2.0, 09/02, page 197 of 366 4.6.6 trap function informs the q2sd of the end of the display list. command format 15 draw mode code 0 1. code b'11111 2. rendering attributes reference data drawing destination multi-valued source binary source binary work specified color rendering work draw mode reserved fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 o: can be used v: can be used (specified color is binary eos bit value) a: referenced depending on mode (valid when work = 1) * : referenced depending on mode (clear to 0 when fst = 1) z: referenced depending on mode (clear to 0 when lni = 1) blank: cannot be used (clear to 0) description halts the drawing operation and sets tra to 1 in the status register (sr). if tre is set to 1 in the interrupt enable register (ier), an interrupt is sent to the superh. this command must be placed at the end of the display list. rev. 2.0, 09/02, page 198 of 366 example display list area drawing starts register setting command drawing command interrupt source tra occurs if tre = 1 at this time, an interrupt is generated externally. drawing command interrupt command drawing command drawing stops . . . rev. 2.0, 09/02, page 199 of 366 section 5 registers 5.1 register map table 5.1 registers 010 012 014 016 018 01a 01c 01e 020 022 024 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w x y 0 1 h l h l l work area start address dma transfer word count display size display start address dma transfer start address display list start address multi-valued source area start address wsar dmawr dsr dsar dmasr dlsar ssar dsx dsy dsa0 dsa1 dlsah dlsal ssah wsah dmash dmasl dmawl 03e 040 r r command status cstr 026 028 02a 02c 02e 030 032 034 036 038 03a 03c r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w horizontal sync pulse width horizontal scan cycle vertical sync position vertical scan cycle horizontal display end position vertical display start position horizontal display start position vertical display end position display off output color detection l h l h h l hswr hcr vspr vcr dswr door cder hds hde vds vde hsw hc vsp vc dor dog dob cdr cdg cdb display window csth cstl 1514131211109876543210 register address 000 002 004 006 008 00a 00c 00e r/w r/w register name abbre- viation r w r/w r/w r/w r/w r/w 1 0 system control status status register clear interrupt enable memory mode display mode rendering mode input data conversion mode sysr sr srcr ier memr dsmr remr iemr a [10:0] 1514131211109876543210 data sres dres den dc rbrk rs tvr frm dmf cer vbk tra csf dbf tvcl frcl dmcl cecl vbcl trcl cscl tve fre dme cee vbe tre cse mwx mat yuv dtp mdtp bg brk femp bre wrap rsae flt ssal wsal dbm0 dbm1 dma0 dma1 daa0 daa1 q0 q1 q2 q3 mes0 tvm0 tvm1 scm0 mes1 scm1 ref3 ref2 ref1 ref0 gbm1 gbm2 gbm0 yuv0 yuv1 brcl rev. 2.0, 09/02, page 200 of 366 table 5.1 registers (cont) vsal2 vid1 blinka blinkb vsiz4 hcs1 hcs2 vcs1 vinm oden1 rgb vsah2 vsizex vsizey vie vsal1 vsah1 vcs2 csarh1 csarh2 csarl1 csarl2 r/w r/w 052 054 056 058 05a 05c to 060 062 064 066 068 06a 06c 06e 070 072 074 076 078 07a 07c 07e r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w equalizing pulse width separation width display mode 2 video display start position video incorporation mode cursor display start position cursor area start address reserved video area start address video window size vpr eqw spw cded pri2 vwry hdis odev pri vwe vvp vsal0 vsah0 fbd ce2 ce1 csy1 hvp eqwr spwr dsmr2 vsar vsizer vimr csr csar 050 r/w w r/w 1514131211109876543210 register address 042 044 046 048 04a r/w r/w register name abbre- viation r/w cs1 0 image data transfer start address image data size image data entry dma transfer word count ider a [10:0] 1514131211109876543210 dmawh data isah isal idsx bgsx bgsy idsy ide h h l x y isar r/w r/w 04c 04e r/w background start coordinate x y bgsr dmawr idsr vid0 vsiz3 vsiz2 vsiz1 vsiz0 oden0 csy0 rev. 2.0, 09/02, page 201 of 366 table 5.1 registers (cont) 200 202 204 206 208 20a 5ec 5fe r/w r/w r/w r/w r/w r/w r/w r/w color palette cp000r cp001r cp255r cp002r r000 b000 r001 b001 b002 r002 r255 b255 g000 g001 g002 g255 000h 000l 001h 001l 002h 002l 255h 255l 09c to 1fe reserved 080 082 084 086 088 08a 08c 08e 090 092 094 096 r r r r r r r r r r r/w r/w 0 ymax xmax h l 098 r/w ymin xmin xmax ymax y x x y sclr rtnr rsar xc yc xo yo uxmin uymin uxmax uymax sxmax symax rtnl rtnh rsa user clipping area local offset current pointer system clipping area return address rendering start address 09a r/w color coofr coofg coofb color offset uclr curr lcor 1514131211109876543210 register address r/w register name abbre- viation cs1 a [10:0] 1514131211109876543210 data reserved 600to 7fe rev. 2.0, 09/02, page 202 of 366 5.2 interface control registers the interface control registers are registers related to overall q2sd control, mapped onto addresses (a10 to a1) h'000 to h'00e, h056, and h072. system control register ( sysr) status register (sr) status register clear register (srcr) interrupt enable register (ier) memory mode register (memr) display mode register (dsmr) display mode 2 register (dsmr2) rendering mode register (remr) input data conversion mode register (iemr) video incorporation mode register (vimr) rev. 2.0, 09/02, page 203 of 366 5.2.1 system control register (sysr) the system control register ( sysr) specifies q2sd system operation. the sysr is in itialized as follows in a reset: bits sres and dres are set to 1. bits den, rbrk, dc, rs, dma1, dma0, daa1, and daa0 are cleared to 0. bits dbm1 and dbm0 retain their values. register address: h'000 bit bit name initial value r/w description 15 sres 1 r/w software reset (sres) controls execution and suspension of command processing. 0: command processing execution is enabled. 1: sres is set to 1 when a hardware reset is performed. clear to 0 in initialization. when this bit is set to 1 by software, a reset is performed for drawing operations only. in this case, the bit must be set to 1 for at least 16 system operating clock cycles. when sres is set to 1, the command error flag (cer), trap flag (tra), command suspend flag (csf), rendering break bit (rbrk), and drawing break flag (brk) are cleared to 0. rev. 2.0, 09/02, page 204 of 366 bit bit name initial value r/w description 14 13 dres den 1 0 r/w r/w display reset (dres) display enable (den) these bits control starting and stopping of display synchronous operation. 00: display operation is started. the dres bit cannot be cleared to 0 while the 5(6(7 pin is low. when using the q2sd from the initial state, make all control register settings before clearing the dres bit to 0. when the den bit is 0, display data has the value set in the display off output register. 01: display operation is started. the dres bit cannot be cleared to 0 while the 5(6(7 pin is low. when using the q2sd from the initial state, make all control register settings, clear the dres bit to 0, and then set the den bit to 1. display data has the value stored in the ugm from the next frame. 10: display synchronous operation is started. the q2sd only performs ugm refresh operations, regardless of the setting of tvm1 and tvm0 in the display mode register. with these settings, the q2sd operates as shown below. when switching from dres, den = 01 to dres, den = 10, the setting dres, den = 11 occurs temporarily for reasons relating to internal updating, but this does not affect operation. 1. drawing is not performed even if the rs bit is set to 1 in sysr. 2. display data is all-0 output. 3. the vbk flag is cleared to 0 in sr. 4. except during video incorporation (vie = 1), waits are output continuously when ugm access is performed by the cpu or dma controller. 11: setting prohibited 12, 11 ??? reserved only 0 should be written to these bits. rev. 2.0, 09/02, page 205 of 366 bit bit name initial value r/w description 10 rbrk 0 r/w rendering break (rbrk) controls rendering (drawing) breaks. this bit should only be set when the brk bit is cleared to 0. 0: the tra bit in the status register (sr) is set to 1 by trap command execution, and drawing is terminated. 1: the currently executing command ends while the q2sd is performing drawing, and when the next command is fetched the brk bit in the status register (sr) is set to 1 and drawing enters the terminated state. the brk bit does not change if this bit is set to 1 while the q2sd is not performing drawing. after the break, the start address of the next command is placed in the command status register (cstr). this bit is cleared to 0 only when a drawing break is effected. 9 dc 0 r/w display area change (dc) controls frame buffer switching in manual display change mode. 0: switching of the frame buffer for display is not performed in manual display change mode. when the dc bit is 0, it can be set to 1. 1: switching of the frame buffer for display is performed in manual display change mode. this bit can be set to 1 set only when it is 0. switching is performed in frame units in non- interlace and interlace modes, and in field units in interlace sync & video mode. this bit is cleared to 0 after frame buffer switching, and so should not be cleared to 0 by the superh. rev. 2.0, 09/02, page 206 of 366 bit bit name initial value r/w description 8 rs 0 r/w rendering start (rs) specifies the start of rendering. 0: rendering is not started. 1: rendering is started. this bit is cleared to 0 after rendering starts. when this bit is set to 1, all the data held in the fifo in the cpu interface unit is stored in the ugm. all the data held in the fifo is also stored in the ugm when the superh does not access the ugm for 32 tcyc0 or longer, and when the superh reads the ugm. 7 6 dbm1 dbm0 * * r/w r/w double-buffer mode 1 and 0 (dbm1, dbm0) these bits select double-buffer control. 00: auto display change mode is set. 01: auto rendering mode is set. 10: manual display change mode is set. 11: setting prohibited rev. 2.0, 09/02, page 207 of 366 bit bit name initial value r/w description 5 4 dma1 dma0 0 0 r/w r/w dma mode (dma1, dma0) these bits specify dma transfer. use the dma flag (dmf) in the status register (sr) to check for the beginning and end of dma mode. 00: normal mode is set. if dma transfer is in progress at this time, the transfer data is not guaranteed. 01: the mode for dma transfer to memory (ugm) corresponding to &6 is set. when the remaining dma transfer count reaches 0, this bit is automatically cleared and normal mode is entered. the initial value of the remaining dma transfer count is determined by the setting in the dma transfer word count register (dmawr). the remaining dma transfer count is an internal value in the lsi, and is decremented by 1 each time a word is processed. do not perform ugm access by the cpu in this mode. if normal mode (dma1 = 0, dma0 = 0) is set by the superh in this mode, dma transfer will be aborted. as the value of the transfer data at the time of the abort is undefined, if an abort is performed, dma transfer must be started over again from the beginning. 10: setting prohibited 11: the mode for dma transfer to the register [image data entry register (ider)] corresponding to &6 is set. in this mode, register address incrementing is not performed and all writes are to ider. when the remaining dma transfer count reaches 0, this bit is automatically cleared and normal mode is entered. the initial value of the remaining dma transfer count is determined by the setting in the dma transfer word count register (dmawr). the remaining dma transfer count is an lsi internal value, and is decremented by 1 each time a word is processed. do not perform ugm access by the cpu in this mode. if normal mode (dma1 = 0, dma0 =0) is set by the superh in this mode, dma transfer will be aborted. as the value of the transfer data at the time of the abort is undefined, if an abort is performed, dma transfer must be started over again from the beginning. rev. 2.0, 09/02, page 208 of 366 bit bit name initial value r/w description 3 2 daa1 daa0 0 0 r/w r/w dma address mode (daa1, daa0) sets the address mode for dma transfer. 00: single address mode, data is latched at the rising edge of the 5' signal or the '$&. signal, whichever comes first. 01: single address mode, with data latched at the rise of the '$&. signal. the 5' signal is ignored. 10: dual address mode 11: setting prohibited 1, 0 ??? reserved the write value should always be 0. note: * value is retained. rev. 2.0, 09/02, page 209 of 366 5.2.2 status register (sr) the status register (sr) is used to read the internal status of the q2sd from outside. the sr is initialized as follows in a reset: the dbf flag retains its value. the q flags are set to 0100. the femp flag is set to 1. all other flags are cleared to 0. register address: h'002 bit bit name initial value r/w description 15 tvr 0 r tv sync signal error flag (tvr) flag that indicates that (;96<1& has been detected within the vertical cycle. 0: the rise of (;96<1& has been detected each time within the vertical cycle determined by the vertical scan cycle register (vcr) setting after the tvr flag has been cleared by the dres bit in sysr or the tvcl bit in srcr. 1: in tv sync mode (bits tvm1 and tvm0 = 10 in dsmr), a rise of (;96<1& has not been detected within the vertical cycle determined by the vcr set value. the tvr flag retains its state until cleared by a reset or by software. 14 frm 0 r frame flag (frm) flag that indicates the vertical blanking interval after frame display. 0: indicates the interval from frm flag clearing by the dres bit in sysr or the frcl bit in srcr until the end of the next display in non-interlace mode, or until the end of the next even field display in interlace mode or interlace sync & video mode. 1: indicates the interval from the first even field vertical blanking interval after frm flag clearing by the dres bit in sysr or the frcl bit in srcr until the frm flag is cleared again (switched in frame units). rev. 2.0, 09/02, page 210 of 366 bit bit name initial value r/w description 13 dmf 0 r dma flag (dmf) flag that indicates that dma transfer mode has been initiated and transfer has been completed. 0: dma transfer mode has not been initiated at all since dmf flag clearing by the dmcl bit in srcr, or the next dma transfer mode (bits dma1 and dma0 = 01 or 11 in sysr) has been initiated and the remaining transfer count has not yet reached 0. 1: dma transfer mode has been initiated and the transfer word count has reached 0. the dmf flag retains its state until cleared by a reset or by software. 12 cer 0 r command error flag (cer) flag that indicates that an illegal command has been fetched. 0: normal state. an illegal command has not been fetched since cer flag clearing by the sres bit in sysr or the cecl bit in srcr. an illegal command is one in which the upper 5 bits of the command code are undefined. the q2sd does not check the legality of the rendering attributes in the lower 11 bits. 1: drawing operation halt state. drawing operation remains halted because an illegal command was fetched after cer flag clearing by the sres bit in sysr or the cecl bit in srcr. the cer flag retains its state until cleared by a reset or by software. 11 vbk 0 r vertical blanking flag (vbk) flag that indicates the vertical blanking interval. 0: indicates the interval from vbk flag clearing by the dres bit in sysr or the vbcl bit in srcr until the end of the next display. 1: indicates the interval from the first vertical blanking interval after vbk flag clearing by the dres bit in sysr or the vbcl bit in srcr until the vbk flag is cleared again (switched in field units). rev. 2.0, 09/02, page 211 of 366 bit bit name initial value r/w description 10 tra 0 r trap flag (tra) flag that indicates the end of command execution. 0: indicates the interval from tra flag clearing by the sres bit in sysr or the trcl bit in srcr until the end of execution of the next command. 1: command execution has ended, or the current command is not being executed. the tra flag retains its state until cleared by a reset or by software. 9 csf 0 r command suspend flag (csf) flag that indicates that command execution has been suspended due to a frame change in auto display change mode or manual display change mode. 0: normal operation 1: a rendering end interrupt has not been generated in the interval from csf flag clearing by the sres bit in sysr or the cscl bit in srcr until the next frame change. the csf flag retains its state until cleared by a reset or by software. 8dbf * r display buffer frame (dbf) flag that indicates the display start address register used as the display start address by the q2sd. 0: address indicated by dsar0 is being used as display start address. 1: address indicated by dsar1 is being used as display start address. 7 brk 0 r drawing break flag (brk) flag that indicates a drawing break. 0: indicates the interval until the next drawing break occurs after the brk flag is cleared by the sres bit in sysr or the brcl bit in srcr. 1: indicates that a command is not currently being executed due to a drawing break directive. the brk flag retains its state until cleared by a reset or by software. rev. 2.0, 09/02, page 212 of 366 bit bit name initial value r/w description 6 femp 1 r fifo empty flag (femp) transfer data from the cpu to the ugm is temporarily stored in a fifo. these transfers include ugm writes and data transfers via idr. this flag indicates whether there is ugm storage data in the fifo. 0: there is ugm storage data in the fifo. 1: there is no ugm storage data in the fifo. 5, 4 ??? reserved these bits always read 0. 3 2 1 0 q3 q2 q1 q0 0 1 0 0 r r r r q flags (q3 to q0) flags used for q2sd series product identification. in the q2sd, these flags read 0100. 0010: hd64411 (q2) 0011: hd64412 (q2i) 0100: hd64413a (q2sd) note: * value is retained. rev. 2.0, 09/02, page 213 of 366 5.2.3 status register clear register (srcr) the status register clear register (srcr) clears the corresponding flags in the status register (sr). writing 1 to one of bits 15 to 9 or 7 in the srcr register will clear the corresponding flag in sr to 0. when sr clearing is completed, the value of the srcr register is cleared to all-0 internally (a read will return 0). register address: h'004 bit bit name abbreviation description 15 tv sync signal error flag clear tvcl writing 1 to the tcvl bit clears the tvr flag to 0 in sr. 14 frame buffer clear frcl writing 1 to the frcl bit clears the frm flag to 0 in sr. 13 dma flag clear dmcl writing 1 to the dmcl bit clears the dmf flag to 0 in sr. 12 command error flag clear cecl writing 1 to the cecl bit clears the cer flag to 0 in sr. 11 vertical blanking flag clear vbcl writing 1 to the vbcl bit clears the vbk flag to 0 in sr. 10 trap flag clear trcl writing 1 to the trcl bit clears the tra flag to 0 in sr. 9 command suspend flag clear cscl writing 1 to the cscl bit clears the csf flag to 0 in sr. 8 reserved only 0 should be written to this bit. 7 drawing break flag clear brcl writing 1 to the brcl bit clears the brk flag to 0 in sr. 6 to 0 reserved only 0 should be written to these bits. note: * value is retained. rev. 2.0, 09/02, page 214 of 366 5.2.4 interrupt enable register (ier) the interrupt enable register (ier) enables or disables interrupts by the corresponding flags in the status register (sr). when a bit in sr is set to 1 and the bit at the corresponding bit position in the ier register is also 1, ,5/ is driven low and an interrupt request is sent to the cpu. the interrupt generation condition is as follows. interrupt generation condition = ,5/ = defghij a = tvr tve b = frm fre c = dmf dme d = cer cee e = vbk vbe f = tra tre g = csf cse h = brk bre register address: h'006 bit bit name initial value r/w description 15 tve 0 r/w tv sync signal error flag enable (tve) enables or disables interrupts initiated by the tvr flag in sr. 0: interrupts initiated by the tvr flag in sr are disabled. 1: interrupts initiated by the tvr flag in sr are enabled. when tvr tve = 1, an ,5/ interrupt request is sent to the cpu. 14 fre 0 r/w frame flag enable (fre) enables or disables interrupts initiated by the frm flag in sr. 0: interrupts initiated by the frm flag in sr are disabled. 1: interrupts initiated by the frm flag in sr are enabled. when frm fre = 1, an ,5/ interrupt request is sent to the cpu. rev. 2.0, 09/02, page 215 of 366 bit bit name initial value r/w description 13 dme 0 r/w dma flag enable (dme) enables or disables interrupts initiated by the dmf flag in sr. 0: interrupts initiated by the dmf flag in sr are disabled. 1: interrupts initiated by the dmf flag in sr are enabled. when dmf dme = 1, an ,5/ interrupt request is sent to the cpu. 12 cee 0 r/w command error flag enable (cee) enables or disables interrupts initiated by the cer flag in sr. 0: interrupts initiated by the cer flag in sr are disabled. 1: interrupts initiated by the cer flag in sr are enabled. when cer cee = 1, an ,5/ interrupt request is sent to the cpu. 11 vbe 0 r/w vertical blanking flag enable (vbe) enables or disables interrupts initiated by the vbk flag in sr. 0: interrupts initiated by the vbk flag in sr are disabled. 1: interrupts initiated by the vbk flag in sr are enabled. when vbk vbe = 1, an ,5/ interrupt request is sent to the cpu. 10 tre 0 r/w trap flag enable (tre) enables or disables interrupts initiated by the tra flag in sr. 0: interrupts initiated by the tra flag in sr are disabled. 1: interrupts initiated by the tra flag in sr are enabled. when tra tre = 1, an ,5/ interrupt request is sent to the cpu. 9 cse 0 r/w command suspend flag enable (cse) enables or disables interrupts initiated by the csf flag in sr. 0: interrupts initiated by the csf flag in sr are disabled. 1: interrupts initiated by the csf flag in sr are enabled. when csf cse = 1, an ,5/ interrupt request is sent to the cpu. rev. 2 . 0, 09 / 02, page 216 of 366 b i t b i t na m e i n iti a l va l ue r / w descr i p t i on 8 ? ? ? re s e r v ed o nly 0 should be w r i tt en t o t h is bi t . 7 bre 0 r / w d r awing b r eak flag enable ( bre) enables or disables in t e rr up t s ini t ia t ed by t he brk f lag in sr. 0: i n t e rr up t s ini t ia t ed by t he brk f lag in sr a r e disabled. 1: i n t e rr up t s ini t ia t ed by t he brk f lag in sr a r e enabled. when brk bre = 1, an ,5/ i n t e rr up t r equest is sent t o t he cpu. 6 t o 0 ? ? ? re s e r v ed o nly 0 should be w r i tt en t o t hese bi t s. 5.2.5 memory mode register (memr) the memory mode regi s ter ( m e m r) s pecifie s the s ize o f ugm us e d a nd t he memory acce s s timing. if the value of thi s regi s ter i s modified during a memory acce s s , operation w ill be temporarily un s table. the m e m r bit s m e s 1, m e s 0, and ma t are initialized to 0 by a re s et. r e g i st e r add re ss: h' 008 b i t b i t na m e i n iti a l va l ue r / w descr i p t i on 15 t o 6 ? ? ? re s e r v ed o nly 0 should be w r i tt en t o t hese bi t s. 5 4 m es1 m es0 0 0 r / w r / w m e m o ry s i z e (m es 1 , m es 0 ) these bi t s select t he size and quan t i t y of m e m o r ies used f o r t he u g m . 00: o ne 16 -m b it ( 16) m e m o r y, 16 - bit bus 01: two 16 -m bit ( 16) m e m o r ies, 32 - bit bus 10: o ne 64 - m bit ( 16) m e m o r y, 16 - bit bus 11: o ne 64 - m bit ( 32) m e m o r y, 32 - bit bus rev. 2.0, 09/02, page 217 of 366 bit bit name initial value r/w description 3 to 1 ??? reserved only 0 should be written to these bits. 0 mat 0 r/w memory access timing (mat) sets the ugm access timing. apl (active precharge latency) 0: 5 1: 5 pl (precharge latency) 0: 3 1: 2 pcl (ras-cas latency) 0: 3 1: 2 wpl (write precharge latency) 0: 2 1: 2 rev. 2.0, 09/02, page 218 of 366 5.2.6 display mode register (dsmr) the display mode register (dsmr) specifies q2sd display operations. if the value of this register is modified during a display operation, operation will be temporarily unstable. the dsmr is in itialized as follows in a reset: bits wrap and bg are initialized to 0, bits tvm1 and tvm0 to 10, and bits ref3 to ref0 to 1000. the scm1 and scm0 bits retain their values. register address: h'005 bit bit name initial value r/w description 15 flt 0 r/w filter mode (flt) 0: fg and bg pixel data is output for display as the respective screens. 1: fg and bg pixel data is averaged and output for display as the fg screen. set gbm = 001/101, vwe = 0, pri = 00, fbd = 0, scm = 11. fg transparent color determination is not performed. transparent color determination (cde) is performed on the result. set the bg start position one line below the fg start position. the average is found by right-shifting the result of addition of each part in 16-bit format (5:6:5). a fraction of a shift is ignored. 14 to 12 ??? reserved only 0 should be written to these bits. rev. 2.0, 09/02, page 219 of 366 bit bit name initial value r/w description 11 warp 0 r/w background screen wraparound mode configuration (wrap) 0: background screen wraparound is not performed. display contents are not guaranteed if the display area extends beyond the memory installation space. 1: background screen wraparound is performed. the wraparound units are the number of pixels specified by the mwx bit in the rendering mode register (remr) in the x direction, and 512 pixels in the y direction. the start coordinates of this area are indicated by bits 13 to 9 of the background start coordinate register (bgsr). 10 bg 0 r/w background screen combination (bg) 0: background screen combination is not performed. 1: background screen combination is performed. 9, 8 ??? reserved only 0 should be written to these bits. rev. 2.0, 09/02, page 220 of 366 bit bit name initial value r/w description 7 6 tvm1 tvm0 1 0 r/w r/w tv sync mode (tvm1, tvm0) these bits specify tv sync mode, in which synchronous operation is performed by means of (;+6<1& and (;96<1& input from an external source, or master mode, in which +6<1& and 96<1& are output. 00: master mode is set. the q2sd outputs +6<1& , 96<1& , and 2'') signals. in this mode, when csy1 = 1 in display mode register 2 (dsmr2), set initial values in the equalizing pulse width register (eqwr) and separation width register (spwr). 01: synchronization system switching mode is set. switching is performed from tv sync mode to master mode, or vice versa, via this mode. in this mode, display operations are forcibly halted and the disp pin output goes low. the clock supply to the clk1 pin can also be stopped (input invalidated) (fixed high within the chip). the +6<1& , 96<1& , and 2'') pins are inputs. 10: tv sync mode is set. (;+6<1& , (;96<1& , and 2'') signals are input to the q2sd. csync output is fixed high. in this mode, clear both csy1 and csy0 to 0 in display mode register 2 (dsmr2). 11: setting prohibited 5 4 scm1 scm0 * * r/w r/w scan mode (scm1, scm0) these bits specify the display output scan mode and the unit of display switching. 00: non-interlace mode: frame buffer switching can be performed in 1-vc units. 01: setting prohibited 10: interlace mode: frame buffer switching can be performed in 2-vc units. 11: interlace sync & video mode: frame buffer switching can be performed in 1-vc units. rev. 2.0, 09/02, page 221 of 366 bit bit name initial value r/w description 3 2 1 0 ref3 ref2 ref1 ref0 1 0 0 0 r/w r/w r/w r/w refresh cycles (ref3 to ref0) these bits specify the number of cycles for which refreshing is performed within one raster in the display screen area. 0000: refresh timing is not output 0001: number of refresh cycles = 1 0010: number of refresh cycles = 2 0011: number of refresh cycles = 3 0100: number of refresh cycles = 4 0101: number of refresh cycles = 5 0110: number of refresh cycles = 6 0111: number of refresh cycles = 7 1000: number of refresh cycles = 8 1001: number of refresh cycles = 9 1010: number of refresh cycles = 10 1011: number of refresh cycles = 11 1100: number of refresh cycles = 12 1101: number of refresh cycles = 13 1110: number of refresh cycles = 14 1111: number of refresh cycles = 15 note: * value is retained. rev. 2.0, 09/02, page 222 of 366 5.2.7 display mode 2 register (dsmr2) the display mode 2 register (dsmr2) specifies q2sd display operations. if the value of this register is modified during a display operation, operation will be temporarily unstable. in a reset, bits csy1 and cys0 retain their values, and the other bits are cleared to 0. register address: h'056 bit bit name initial value r/w description 15 to 13 ??? reserved only 0 should be written to these bits. 12 cded 0 r/w cde disable (cded) controls cde pin output. in tv sync mode (tvm1 = 1, tvm0 = 0), the cde pin is used to switch between external sync signal generation circuit video output and q2sd analog r/g/b output. 0: cde pin output is enabled. 1: cde pin output is disabled. 11 pri2 0 r/w window priority (pri2, pri) these bits set the screen display priority. 10 vwry 0 r/w video window rgb/yc mode (vwry) selects whether the data displayed in the video window is stored in the ugm in rgb format or yc format. 0: video window displays rgb data in the ugm as rgb data. 1: video window displays yc data in the ugm as rgb data. 9 hdis 0 r/w [mode in which foreground screen 1 starts at x = 512 in case of 1024-pixel memory width] (hdis) when hdis = 1, use is possible when gbm = 000 or 001 and rsae = 0. 0: foreground screen 1 starts at x = 0. 1: foreground screen 1 starts at x = 512. rev. 2.0, 09/02, page 223 of 366 bit bit name initial value r/w description 8 odev 0 r/w 2'') signal polarity select (odev): selects the polarity of the 2'') signal. 0: 2'') goes low in first-half field in same frame of interlace display. 1: 2'') goes high in first-half field in same frame of interlace display. 7 6 csy1 csy0 * * r/w r/w &6<1& mode (csy1, csy0) these bits select the &6<1& signal output mode in master mode (tvm1 = 0, tvm0 = 0). when csy1 = 1, values must be set in the equalizing pulse width register (eqwr) and separation width register (spwr). 00: waveform determined by exclusive logical or of 96<1& and +6<1& is output as &6<1& . in tv sync mode (tvm1 = 1, tvm0 = 0), this mode should be selected. 01: setting prohibited 10: equalizing pulses are output in 3-raster period from fall of 96<1& , separation in next 3-raster period, equalizing pulses in next 3-raster period, and +6<1& waveform in other periods. 11: equalizing pulses are output in 2.5-raster period starting 0.5 raster after fall of 96<1& , separation in next 2.5-raster period, equalizing pulses in next 2.5-raster period, and +6<1& waveform in other periods. 5 pri 0 r/w window priority (pri2, pri) these bits set the screen display priority. 00: screen priority order is: cursor 1, cursor 2, foreground, video, background. 01: setting prohibited 10: screen priority order is: cursor 1, foreground, video, cursor 2, background. 11: screen priority order is: foreground, video, cursor 1, cursor 2, background. 4 ??? reserved the write value should always be 0. rev. 2.0, 09/02, page 224 of 366 bit bit name initial value r/w description 3 fbd 0 r/w foreground disable (fbd) selects display or non-display of the foreground screen. 0: foreground screen is displayed. 1: foreground screen is not displayed. 2 ce2 0 r/w cursor 2 enable (ce2) selects display or non-display of cursor 2. 0: cursor 2 is not displayed. 1: cursor 2 is displayed. cursor blinking is always performed. to give the appearance of a non- blinking cursor, make the same setting for cursor blink shapes a and b stored in the cursor area. in q2sd cursor blinking, cursor blink shapes a and b are displayed alternately. to provide a period in which the cursor is not displayed, make one entire waveform a transparent color. 1 ce1 0 r/w cursor 1 enable (ce1) selects display or non-display of cursor 1. 0: cursor 1 is not displayed. 1: cursor 1 is displayed. cursor blinking is always performed. to give the appearance of a non- blinking cursor, make the same setting for cursor blink shapes a and b stored in the cursor area. in q2sd cursor blinking, cursor blink shapes a and b are displayed alternately. to provide a period in which the cursor is not displayed, make one entire waveform a transparent color. 0 vwe 0 r/w video window enable (vwe) selects display or non-display of the video window. 0: video window is not displayed. 1: video window is displayed. the display contents are not guaranteed if this bit is set before vid changes after vie is set to 1. note: * value is retained. rev. 2.0, 09/02, page 225 of 366 5.2.8 rendering mode register (remr) the rendering mode register (remr) specifies q2sd rendering operations. if the value of this register is modified during a drawing operation, operation will be temporarily unstable. the exception is modification by a wpr command from the display list, in which case the following conditions must be satisfied: changing the mwx setting is prohibited. for the gbm bits, only the drawing bit configuration can be changed; changing the display bits is prohibited. rsae can be changed, on condition that the change agrees with the gbm setting. in a reset, the rsae bit in the remr register is cleared to 0, while the mwx and gbm bits retain their values. register address: h'00c bit bit name initial value r/w description 15 rsae 0 r/w drawing start address enable (rsae) allows the drawing area to be set separately from the display area. the start address of a drawing area separate from the display area is set in the drawing start address register (rsar). 0: value in display start address register (dsar) is used for drawing area. when this setting is made, the gbm setting must be 000 or 001. 1: value in rendering start address register (rsar) is used for drawing area. 14 to 7 ??? reserved only 0 should be written to these bits. 6mwx * r/w memory width (mwx) specifies the x-direction logical coordinate space of the ugm connected to the q2sd. 0: x-direction logical coordinate space is 512 pixels 1: x-direction logical coordinate space is 1024 pixels rev. 2.0, 09/02, page 226 of 366 bit bit name initial value r/w description 5 to 3 ??? reserved only 0 should be written to these bits. 2 1 0 gbm2 gbm1 gbm0 * * * r/w r/w r/w graphic bit mode 2 to 0 (gbm2 to gbm0) these bits specify the bit configuration of the rendering data and display data handled by the q2sd. note that the setting of these bits may be linked to the rsae bit setting. note: * value is retained. table 5.2 bit configuration description bit 2: gbm2 bit 1: gbm1 bit 0: gbm0 fg bit configuration bg bit configuration rendering bit configuration rsae bit setting 0 0 0 8 bits/pixel 8 bits/pixel 8 bits/pixel 0 or 1 1 16 bits/pixel 16 bits/pixel 16 bits/pixel 0 or 1 10 8 bits/pixel 16 bits/pixel 8 bits/pixel 0 or 1 1 16 bits/pixel 8 bits/pixel 16 bits/pixel 0 or 1 1 0 0 8 bits/pixel 8 bits/pixel 16 bits/pixel must be 1 1 16 bits/pixel 16 bits/pixel 8 bits/pixel must be 1 10 8 bits/pixel 16 bits/pixel 16 bits/pixel must be 1 1 16 bits/pixel 8 bits/pixel 8 bits/pixel must be 1 rev. 2.0, 09/02, page 227 of 366 5.2.9 input data conversion mode register (iemr) the input data conversion mode register (iemr) specifies the conversion format for input data from the superh. if the value of this register is modified during a data conversion, operation will be temporarily unstable. in a reset, all iemr bits are cleared to 0. register address: h'00e bit bit name initial value r/w description 15 to 5 ??? reserved only 0 should be written to these bits. 4 yuv2 0 r/w yuv mode: this bit specify whether data input in yuv or d yuv format is to be converted to rgb format before being stored in the ugm. 3 mdtp 0 r/w memory data type mode (mdtp) specifies whether byte-unit swapping is to be performed in a word access ugm memory write transfer from the superh. this bit is valid when bits yuv2 to yuv0 are set to 000, and bits dma1 and dma0 are set to either 00 or 01. this bit is invalid for register writes from the superh, and also for ugm memory read operations by the superh. 0: byte-unit swapping is not performed in a word access ugm memory write transfer from the superh. 1: in a word access ugm memory write transfer from the superh, the upper and lower bytes are swapped within the same word (16 bits). rev. 2.0, 09/02, page 228 of 366 bit bit name initial value r/w description 2 dtp 0 r/w data type mode (dtp) specifies whether byte-unit swapping is to be performed in a transfer. this bit is valid for data transfers via the image data entry register (ider). this bit is valid when bits yuv2 to yuv0 are set to 001, 010, 011, or 111, and bits dma1 and dma0 are set to either 00 or 11. 0: byte-unit swapping is not performed in a transfer via ider. 1: in a transfer via ider, the upper and lower bytes are swapped within the same word (16 bits). 1 0 yuv1 yuv0 0 0 r/w r/w yuv mode: these bits specify whether data input in yuv or d yuv format is to be converted to rgb format before being stored in the ugm. rev. 2.0, 09/02, page 229 of 366 table 5.3 yuv mode setting bit 4 bit 1 bit 0 yuv2 yuv1 yuv0 description 0 0 0 normal mode is set. data transfer via ider is not performed. also used when setting yuv2, 1, 0 to (0, 1, 1). 0 0 1 yuv-rgb conversion is performed. when the total number of data conversion pixels reaches 0, these bits are automatically cleared and normal mode is entered. the total number of data conversion pixels is the product of the idsx and idsy set values in the image data size register (idsr). the total number of data conversion pixels is decremented by 1 in the lsi each time a pixel is processed. do not perform vgm access using the &6 pin in this mode. 010 d yuv-rgb conversion is performed. when the total number of data conversion pixels reaches 0, these bits are automatically cleared and normal mode is entered. the total number of data conversion pixels is the product of the idsx and idsy set values in the image data size register (idsr). the total number of data conversion pixels is decremented by 1 in the lsi each time a pixel is processed. do not perform vgm access using the &6 pin in this mode. 0 1 1 16-bit/pixel data is simply transferred, without conversion. when the total number of data conversion pixels reaches 0, these bits are automatically cleared and normal mode is entered. the total number of data conversion pixels is the product of the idsx and idsy set values in the image data size register (idsr). the total number of data conversion pixels is decremented by 1 in the lsi each time a pixel is processed. do not perform vgm access using the &6 pin in this mode. 1 0 0 used when setting yuv2, 1, 0 to (1, 1, 1). 1 0 1 setting prohibited 1 1 0 setting prohibited 1 1 1 8-bit/pixel data is simply transferred, without conversion. when the total number of data conversion pixels reaches 0, these bits are automatically cleared and normal mode is entered. the total number of data conversion pixels is the product of the idsx and idsy set values in the image data size register (idsr). set the number of transfer words (1/2 the number of pixels) as the idsx value. the total number of data conversion pixels is decremented by 1 in the lsi each time a pixel is processed. do not perform vgm access using the &6 pin in this mode. rev. 2.0, 09/02, page 230 of 366 5.2.10 video incorporation mode register (vimr) the video incorporation mode register (vimr) is used to make various video capture settings. register address: h'072 bit bit name initial value r/w description 15 14 vid1 vid0 1 1 r r video window status (vid1, vid0) these bits are status flags that indicate the video area storing the most recent image incorporated from the video input. note that these bits are different in nature from the other bits in this register. the value of these bits is significant only when the vie bit is cleared to 0. note that the meaning of these bits is not guaranteed if video capture proceeds while the vie bit is set to 1. only 00 should be written to these bits (although the write value is ignored). the meaning of the values read from these bits is shown below. 00: most recent image is in video area 0. when video window enable (vwe) is 1, video area 0 is displayed. 01: most recent image is in video area 1. when video window enable (vwe) is 1, video area 1 is displayed. 10: most recent image is in video area 2. when video window enable (vwe) is 1, video area 2 is displayed. 11: indicates initial state after a reset. when video window enable (vwe) is 1, video area 0 is displayed. to save or fetch an image as a still picture, video capture must be halted. the sequence of operations is: halt video capture, read the video window status, and fetch the still picture from the relevant area. rev. 2.0, 09/02, page 231 of 366 bit bit name initial value r/w description 13 to 10 ??? reserved only 0 should be written to these bits (a read will return an undefined value). 9 8 7 6 5 vsiz4 vsiz3 vsiz2 vsiz1 vsiz0 0 0 0 0 0 r/w r/w r/w r/w r/w video incorporation reduction (thinning-out) ratio (vsiz4 to vsiz0) these bits set the reduction ratio when performing video capture. see table 5.4. 4 vinm 0 r/w video incorporation mode (vinm) specifies the field order in video capture. 0: field for which 92'' input is low (lines 1, 3, 5, ...) is incorporated first, followed by field for which 92'' input is high (lines 2, 4, 6, ...). 1: field for which 92'' input is high (lines 2, 4, 6, ...) is incorporated first, followed by field for which 92'' input is low (lines 1, 3, 5, ...). rev. 2.0, 09/02, page 232 of 366 bit bit name initial value r/w description 3 2 oden1 oden0 0 0 r/w r/w incorporated field select (oden1, oden0) these bits select the field for which video input scanning method specification and capture are to be performed in video capture. 00: input video is non-interlace. do not input interlace signal. 01: input video is interlace, and frame screens are incorporated with combination of even and odd fields. supplementing is not performed for operation when fields are combined. 10: input video is interlace, and only fields for which 92'' signal is low (odd fields) are incorporated. number of scanning lines of incorporated image is 1/2 number of frame screen scanning lines. 11: input video is interlace, and only fields for which 92'' signal is high (even fields) are incorporated. number of scanning lines of incorporated image is 1/2 number of frame screen scanning lines. the vertical size of video storage area (vsizey) depends on the setting values of oden1 and oden0. oden1 and oden0 are described and the calculation formula of vsizey is shown below: oden1 = 0, oden0 = 0 the timing of specifying the start address of video storage area is in vvs unit, and data is taken in vvs units. vsizey = (number of effective lines existing in 1vvs signals) (video capture thinning rate) oden1 = 0, oden0 = 1 the timing of specifying the start address of video storage area is in 2vvs units, and data of both even and odd-number fields are taken. vsizey = (number of effective lines existing in 2vvs signals) (video capture thinning rate) oden1 = 1 the timing of specifying the start address of video storage area is in 2vvs units, and data of either even or odd-number field is taken. vsizey = (number of effective lines existing in 1vvs signals) (video capture thinning rate) rev. 2.0, 09/02, page 233 of 366 bit bit name initial value r/w description 1 rgb 0 r/w rgb conversion mode (rgb) selects whether rgb conversion is to be performed in video capture. 0: yuv4:2:2 data is stored directly in ugm, without conversion to rgb. this data cannot be used for any purpose except display in the video window. 1: data undergoes rgb conversion and is stored in ugm as rgb data. this data can be used as multi-valued source data. 0 vie 0 r/w video incorporation enable (vie) enables or disables video capture. 0: video capture is not performed. 1: video capture is performed. table 5.4 video incorporation reduction ratio bit 9 bit 8 bit 7 bit 6 vertical reduction ratio horizontal reduction ratio vsiz4 vsiz3 vsiz2 vsiz1 vsiz0 = 0 vsiz0 = 1 00001 1 1/2 1 1 1/3 setting prohibited 10 1 setting prohibited setting prohibited 1 1 setting prohibited setting prohibited 1 0 0 1/2 setting prohibited 1/2 1 1/2 1/3 1/6 1 0 1/2 1/4 setting prohibited 1 1/2 setting prohibited setting prohibited 1 0 0 0 1/3 setting prohibited setting prohibited 1 1/3 1/3 1/6 10 1/3 setting prohibited setting prohibited 1 1/3 setting prohibited setting prohibited 1 0 0 1/4 setting prohibited setting prohibited 1 1/4 setting prohibited 1/6 1 0 1/4 1/4 setting prohibited 1 1/4 setting prohibited setting prohibited rev. 2.0, 09/02, page 234 of 366 5.3 memory control registers the memory control registers are registers related to the unified graphics memory ( ugm) configuration, mapped onto addresses (a10 to a1) h'010 to h'01e, h'04c, h04e, h062 to h070, h07c to h07e, and h098. display size registers (dsr) display address registers (dsar) display list start address registers (dlsar) multi-valued source area start address register (ssar) work area start address register (wsar) background start coordinate registers (bgsr) video area start address registers (vsar) video window size registers (vsizer) cursor area start address register (csar) rendering start address register (rsar) 5.3.1 display size registers ( dsr) the display size registers (dsr) specify the size of the display screen. the number of dots in the horizontal direction is set in dsx, and the number of dots in the ver tical direction in dsy. write 0 to bits that are not used for the dsx and dsy f ields (a read will return an undefined value). the dsx and dsy f ields in the dsr registers retain their values in a reset. register address: h'010 bit bit name initial value r/w description 15 to 10 ??? 9 to 0 ? * r/w dsx register address: h'012 bit bit name initial value r/w description 15 to 9 ??? 8 to 0 ? * r/w dsy note: * value is retained. rev. 2.0, 09/02, page 235 of 366 5.3.2 display address registers (dsar) the display address registers (dsar) sp ecify the memory areas to be used as ugm frame buffers. only the upper 7 bits (a22 to a16) of the start physical address of frame buffer 0 (fb0) are set in the dsa0 f ield in dsar, and only the upper 7 bits (a22 to a16) of the start phys ical address of frame buffer 1 (fb1) are set in the dsa1 f ield in dsar. the display address register whose contents are actually valid as the display start address is the register indicated by the dbf bit in the status register (sr). the display address register whose contents are not valid as the display start address indicates the rendering coordinate origin when rase = 0 in the rendering mode register (remr). when these registers are modified, the new set value becomes valid when an internal update is performed in the case of the display address register whose contents are valid as the display start address, and when an external update (rewrite) is performed in the case of the display address register that indicates the rendering coordinate origin. write 0 to bits that are not used for the dsa0 and dsa1 f ields. the dsa0 and dsa1 f ields in the dsar registers r etain their values in a reset. register address: h'014 bit bit name initial value r/w description 15 to 7 ??? 6 to 0 ? * r/w dsa0 (address a22 to a16 setting) register address: h'016 bit bit name initial value r/w description 15 to 7 ??? 6 to 0 ? * r/w dsa1 (address a22 to a16 setting) note: * value is retained. rev. 2.0, 09/02, page 236 of 366 5.3.3 display list start address registers (dlsar) the display list start address registers (dlsar) specify the memory area to be used as the display list. the dlsah and dlsal f ields in dlsar contain a total of 18 bits, and only the upper bits (a22 to a5) of the start physical address of the display list are set in these fields. write 0 to bits that are not used for the dl sah and dlsal f ields (a read will return an undefined value). the dlsah and dlsa f ields in the dlsar registers retain their values in a reset. register address: h'018 bit bit name initial value r/w description 15 to 7 ??? 6 to 0 ? * r/w dlsah (address a22 to a16 setting) register address: h'01a bit bit name initial value r/w description 15 to 5 ? * r/w dlsal (address a15 to a5 setting) 4 to 0 ??? note: * value is retained. rev. 2.0, 09/02, page 237 of 366 5.3.4 multi-valued source area start address register (ssar) the multi-valued source area start address register (ssar) sp ecifies the memory area to be used as the multi-valued source area. the physical address set in this register will be the origin physical address of the multi-valued coordinate. the upper bits (a22 to a16) of the start physical address of the source area are set in the ssah f ield, and the lower bits (a15 to a13) in the ssal f ield. the settable bit range depends on the highest color representation mode and maximum memory width used in each of the display, drawing, and video areas. in 8-bit/pixel mode with a 512-pixel memory width, all bits can be set. in 8-bit/pixel mode with a 1024-pixel memory width, or 16- bit/pixel mode with a 512-pixel memory width, bit 13 should be cleared to 0. in 16-bit/pixel mode with a 1024-pixel memory width, bits 14 and 13 should be cleared to 0. the ssah and ssal f ields in the ssar register r etain their values in a reset. register address: h'01c bit bit name initial value r/w description 15 to 13 ? * r/w ssal (address a15 to a13 setting) 12 to 7 ??? reserved only 0 should be written to these bits (a read will return an undefined value). 6 to 0 ? * r/w ssah (address a22 to a16 setting) note: * value is retained. rev. 2.0, 09/02, page 238 of 366 5.3.5 work area start address register (wsar) the work area start address register (wsar) specifies the memory area to be used as the work area. the physical address set in this register will be the origin physical address of the work coordinate. the upper bits (a22 to a16) of the start physical address of the work area are set in the wsah f ield, and the lower bits (a15 to a13) in the wsal field. the settable bit range depends on the highest color representation mode and maximum memory width used in each of the display, drawing, and video areas. in 8-bit/pixel mode with a 512-pixel memory width, all bits can be set. in 8-bit/pixel mode with a 1024-pixel memory width, or 16- bit/pixel mode with a 512-pixel memory width, bit 13 should be cleared to 0. in 16-bit/pixel mode with a 1024-pixel memory width, bits 14 and 13 should be cleared to 0. the wsah and wsal f ields in the wsar register retain their values in a reset. register address: h'01e bit bit name initial value r/w description 15 to 13 ? * r/w wsal (address a15 to a13 setting) 12 to 7 ??? reserved only 0 should be written to these bits (a read will return an undefined value). 6 to 0 ? * r/w wsah (address a22 to a16 setting) note: * value is retained. rev. 2.0, 09/02, page 239 of 366 5.3.6 background start coordinate registers (bgsr) the background start coordinate registers (bgsr) specify the background start coordinates in the background screen. the settings should be made so that the background screen does not overlap the frame buffers. write 0 to bits that are not used for the b gsx and bgsy f ields (a read will return an undefined value). the bgsx and bgsy bits in the bgsr registers r etain their values in a reset. register address: h'04c bit bit name initial value r/w description 15 to 10 ??? 9 to 0 ? * r/w bgsx register address: h'04e bit bit name initial value r/w description 15, 14 ??? 13 to 0 ? * r/w bgsy note: * value is retained. rev. 2.0, 09/02, page 240 of 366 5.3.7 video area start address registers (vsar) the video area start address registers (vsar) sp ecify the memory areas used as ugm video areas. only the upper 13 bits (a22 to a10) of the start physical addresses are specified by the video area start address fields ( vsah, vsal). three video storage areas are used, of the size specified by vsizex and vsizey. each area has a memory-unit address layout. vsah0 and vsal0 are bits that sp ecify the start address of video area 0 (v0). vsah1 and vsal1 are bits that sp ecify the start address of video area 1 (v1). vsah2 and vsal2 are bits that sp ecify the start address of video area 2 (v2). when the vie bit in the video incorporation mode register (vimr) is 1, the area in which the most recent image captured by video capture was stored is automatically selected as the area used for display. when the vie bit is 0, the video area holding the most recent image is displayed. new values set when these registers are modified become effective when the display is updated internally in the case of display output, or when the next image is incorporated (at the rising edge of the 996 input) in the case of image capture. write 0 to bits that are not used for vsah0 to vsah2 and vsal0 to vsal2. (a read will return an undefined value). the vsar r etains the values in a reset. vsar0 register address: h'062 bit bit name initial value r/w description 15 to 7 ??? 6 to 0 ? * r/w vsah0 register address: h'064 bit bit name initial value r/w description 15 to 10 ? * r/w vsal0 9 to 0 ??? rev. 2.0, 09/02, page 241 of 366 vsar1 register address: h'066 bit bit name initial value r/w description 15 to 7 ??? 6 to 0 ? * r/w vsah1 register address: h'068 bit bit name initial value r/w description 15 to 10 ? * r/w vsal1 9 to 0 ??? vsar2 register address: h'06a bit bit name initial value r/w description 15 to 7 ??? 6 to 0 ? * r/w vsah2 register address: h'06c bit bit name initial value r/w description 15 to 10 ? * r/w vsal2 9 to 0 ??? note: * value is retained. rev. 2.0, 09/02, page 242 of 366 5.3.8 video window size registers ( vsizer) the video window size registers (vsizer) specify the video window display size. set the value obtained by multiplying the number of effective pixels input from off-chip by the reduction (thinning-out) ratio, vsiz, at the time of capture. set 0 for the least significant bits of x and y as shown in the register diagram. this makes the set values of vsizex and vsizey even numbers. write 0 to bits that are not used for the vsizex and vsizey fields (a read will return an undefined value). the vsizer retain their values in a reset. register address: h'06e bit bit name initial value r/w description 15 to 10 ??? 9 to 1 ? * r/w vsizex 0 ??? register address: h'070 bit bit name initial value r/w description 15 to 9 ? * r/w 8 to 1 ??? vsizey 0 ??? note: * value is retained. rev. 2.0, 09/02, page 243 of 366 5.3.9 cursor area start address register (csar) the cursor area start address registers (csar) specify the memory areas used as cursor areas in the ugm. the upper bits (a22 to a16) of the start phys ical address of the cursor area are set in the cursor area start address high (csah) f ield, and the lower bits (a15 to a11) in the cursor area start address low (csal) field. set the cursor a shape in the 1024 bytes from the set address, and the cursor b shape in the next 1024 bytes. the new values set when these registers are modified become effective when internal updating is performed. cursor display data should be set in linear address data format. the csal1, csal2, csah1, and csah2 f ields in the csar registers retain their values in a reset. the cursor 1 area start addresses are set in csah1 and csal1. the cursor 2 area start addresses are set in cash2 and csal2. csar1 register address: h'07c bit bit name initial value r/w description 15 to 11 ? * r/w csal1 (address a15 to a11 setting) 10 to 7 ??? reserved only 0 should be written to these bits (a read will return an undefined value). 6 to 0 ? * r/w csah1 (address a22 to a11 setting) rev. 2.0, 09/02, page 244 of 366 csar2 register address: h'07e bit bit name initial value r/w description 15 to 11 ? * r/w csal2 (address a15 to a11 setting) 10 to 7 ??? reserved only 0 should be written to these bits (a read will return an undefined value). 6 to 0 ? * r/w csah2 (address a22 to a16 setting) note: * value is retained. 5.3.10 rendering start address register (rsar) the rendering start address register (rsar) specifies the start address of the rendering area that is valid when the rsae bit is set to 1 in the rendering mode register (remr). only the upper 7 bits (a22 to a16) of the start physical address of the rendering area are set in the rsa field. the rsa field in the rsar register retains its value in a reset. register address: h'098 bit bit name initial value r/w description 15 to 7 ??? reserved only 0 should be written to these bits (a read will return an undefined value). 6 to 0 ? * r/w rsa (address a22 to a16 setting) note: * value is retained. 5.4 display control registers the display control registers are used to set the display timing, and are mapped onto addresses (a10 to a1) h'026 to h'03c, h052 to h054, h058 to h05a, h074 to h07a, and h200 to h5fe. display window registers (dswr) horizontal sync pulse width register (hswr) horizontal scan cycle register (hcr) rev. 2.0, 09/02, page 245 of 366 vertical start position register ( vspr) vertical scan cycle register (vcr) display off output registers (door) color detection registers (cder) equalizing pulse width register (eqwr) separation width register (spwr) video display start position registers (vpr) cursor display start position registers (csr) color palette registers (cp000r to cp255r) 5.4.1 display window registers (dswr) the display window registers (dswr) specify the horizontal and vertical output timing for the display screen. 1. horizontal display start position ( hds f ields) field that specifies the horizontal display start position in dot-clock units. 2. horizontal display end position (hde fields) field that specifies the horizontal display end position in dot-clock units. 3. vertical display start position ( vds f ields) field that specifies the vertical display start position in raster-line units. 4. vertical display end position (vde fields) field that specifies the vertical display end position in raster-line units. write 0 to bits that are not used for the hds, hde, vds, and vde f ields (a read will return an undefined value). the hds, hde, vds, and vde f ields in the dswr registers retain their values in a reset. rev. 2.0, 09/02, page 246 of 366 register address: h'026 bit bit name initial value r/w description 15 to 9 ??? 8 to 0 ? * r/w hds register address: h'028 bit bit name initial value r/w description 15 to 10 ??? 9 to 0 ? * r/w hde register address: h'02a bit bit name initial value r/w description 15 to 9 ??? 8 to 0 ? * r/w vds register address: h'02c bit bit name initial value r/w description 15 to 10 ??? 9 to 0 ? * r/w vde note: * value is retained. rev. 2.0, 09/02, page 247 of 366 5.4.2 horizontal sync pulse width register (hswr) the horizontal sync pulse width register (hswr) specifies the horizontal signal low-level pulse width in dot-clock units. the hsw bits in the hswr register retain their values in a reset. register address: h'02e bit bit name initial value r/w description 15 to 7 ??? reserved. only 0 should be written to these bits (a read will return an undefined value). 6 to 0 ? * r/w hsw note: * value is retained. 5.4.3 horizontal scan cycle register (hcr) the horizontal scan cycle register (hcr) specifies the horizontal scan cycle in dot-clock units. in tv sync mode (bits tvm1 and tvm0 set to 10 in dsmr), this register setting must be made so that the +6<1& cycle specified by this register is the same as or greater than the (;+6<1& cycle. the hc bits in the hcr register retain their values in a reset. register address: h'030 bit bit name initial value r/w description 15 to 11 ??? reserved. only 0 should be written to these bits (a read will return an undefined value). 10 to 0 ? * r/w hc note: * value is retained. 5.4.4 vertical start position register (vspr) the vertical start position register ( vspr) specifies the vertical sync signal start position in raster-line units. in tv sync mode (tvm1 = 1, tvm0 = 0 in dsmr), this register setting must be made so that the 96<1& fall setting position specified by this register is the same as or later than the fall of (;96<1& . rev. 2.0, 09/02, page 248 of 366 the vsp bits in the vspr register r etain their values in a reset. register address: h'032 bit bit name initial value r/w description 15 to 10 ??? reserved. only 0 should be written to these bits (a read will return an undefined value). 9 to 0 ? * r/w vsp note: * value is retained. 5.4.5 vertical scan cycle register ( vcr) the vertical scan cycle register (vcr) specifies the vertical scan interval, including the vertical retrace line interval, in raster-line units. in tv sync mode (tvm1 = 1, tvm0 = 0 in dsmr), set this register so that the 96<1& rise position set with this register is the same as, or later than, the rise of (;96<1& . if a rise of (;96<1& is not detected within the vertical scan interval set in this register, the tvr flag in the status register (sr) will be set to 1. the vc bits in the vcr register retain their values in a reset. rev. 2.0, 09/02, page 249 of 366 register address: h'034 bit bit name initial value r/w description 15 to 10 ??? reserved. only 0 should be written to these bits (a read will return an undefined value). 9 to 0 ? * r/w vc note: * value is retained. 5.4.6 display off output registers (door) the display off output registers (door) sp ecify the display data to be output when display is off. a 6-bit setting is made for each of the rgb components, in the dor fields, dog f ields, and dob fields. write 0 to bits that are not used for the dor, dog, and dob f ields. the dor, dog, and dob f ields in the door registers r etain their values in a reset. register address: h'036 bit bit name initial value r/w description 15 to 8 ??? 7 to 2 ? * r/w dor 1, 0 ??? register address: h'038 bit bit name initial value r/w description 15 to 10 ? * r/w dog 9, 8 ??? 7 to 2 ? * r/w dob 1, 0 ??? note: * value is retained. rev. 2.0, 09/02, page 250 of 366 5.4.7 color detection registers (cder) the color detection registers (cder) output 1 from the cde pin, when the output color data (dd17 to dd0) matches the values set in these registers. for details of the output color data format, see section 3.2.11, q2sd internal data format. the cdr fields in these registers is compared with dd17 to dd12, the cdg field with dd11 to dd6, and the cdb field with dd5 to dd0. as the display data is all-0 outside the display interval, if an all-0 setting is made in cder, 1 will be output from the cde pin outside the display interval. write 0 to bits that are not used for the cdr, cdb, and cdg fields. the cdr, cdg, and cdb fields in the cder registers retain their values in a reset. register address: h'03a bit bit name initial value r/w description 15 to 8 ??? 7 to 2 ? * r/w cdr 1, 0 ??? register address: h'03c bit bit name initial value r/w description 15 to 10 ? * r/w cdg 9, 8 ??? 7 to 2 ? * r/w cdb 1, 0 ??? note: * value is retained. 5.4.8 equalizing pulse width register (eqwr) the equalizing pulse width register (eqwr) specifies the low-level pulse width of &6<1& signal equalizing pulses in dot-clock units. equalizing pulses are generated at the start and in the middle of each raster. this register is valid when cys1 is set to 1 in display mode 2 register ( dsmr2). the eqw bits in the eqwr register retain their values in a reset. rev. 2.0, 09/02, page 251 of 366 for example, in the case of the ntsc specification, the low-level pulse width is approximately 2.4 s. if the display operating clock frequency is 14.31818 mhz, a value of 2.4 s 14.31818 mhz = 35 should be set in this register. register address: h'052 bit bit name initial value r/w description 15 to 7 ??? reserved. only 0 should be written to these bits (a read will return an undefined value). 6 to 0 ? * r/w eqw note: * value is retained. 5.4.9 separation width register (spwr) the separation width register (spwr) specifies the low-level pulse width of &6<1& signal separation pulses in dot-clock units. separation pulses are generated at the start and in the middle of each raster. set an spw value of less than 1/2 the horizontal scan interval. this register is valid when cys1 is set to 1 in display mode 2 register ( dsmr2). the spw bits in the spwr register retain their values in a reset. if hc is the horizontal scan interval, in the case of the ntsc specification, for example, the separation pulse low width is approximately hc/2 C 4.7 s. if hc is 63.555 s and the display operating clock frequency is 14.31818 mhz, a value of (63.555 s/2 C 4.7s) 14.31818 mhz = 357 should be set in this register. rev. 2.0, 09/02, page 252 of 366 register address: h'054 bit bit name initial value r/w description 15 to 10 ??? reserved. only 0 should be written to these bits (a read will return an undefined value). 9 to 0 ? * r/w spw note: * value is retained. 5.4.10 video display start position registers (vpr) the video display start position registers (vpr) specify the video horizontal and vertical output timing. 1. video horizontal display start position ( hvp f ields) this field sets the video horizontal start position in dot-clock units. 2. video vertical display start position ( vvp f ields) this field sets the video vertical start position in raster-line units. when the scm1 and scm0 bits in the display mode register (dsmr) are set to 11 or 10 (interlace sync & video mode or interlace mode), bit 0 in vvp f ields should be cleared to 0. set the start position so that the video display area does not extend beyond the frame buffer display screen. unlike the hds and vds f ields in the display window registers (dswr), the screen coordinate upper-left reference values should be set in the hvp and vvp f ields. in the horizontal direction the upper-left point is 0, and the right direction is positive, with changes made one by one in dot units. in the vertical direction the upper-left point is 0, and the downward direction is positive, with changes made one by one in line units. write 0 to bits that are not used for the hvp and vvp f ields (a read will return an undefined value). the hvp and vvp bits in the vpr (hvp/vvp) registers r etain their values in a reset. register address: h'058 bit bit name initial value r/w description 15 to 10 ??? 9 to 0 ? * r/w hvp rev. 2.0, 09/02, page 253 of 366 register address: h'05a bit bit name initial value r/w description 15 to 9 ??? 8 to 0 ? * r/w vvp note: * value is retained. 5.4.11 cursor display start position registers (csr) the cursor display start position registers (csr) specify the cursor 1 and 2 horizontal and vertical output timing and the length of the cursor blink shape a and b display intervals. 1. cursor 1 horizontal display start position (hcs1) these bits set the cursor 1 horizontal display start position in dot-clock units. 2. cursor 1 vertical display start position (vcs1) these bits set the cursor 1 vertical display start position in raster-line units. 3. cursor 2 horizontal display start position (hcs2) these bits set the cursor 2 horizontal display start position in dot-clock units. 4. cursor 2 vertical display start position (vcs2) these bits set the cursor 2 vertical display start position in raster-line units. 5. cursor blink shape a display interval length (blnka) these bits set, in field units, the length of the interval during which cursor shape a (stored in the cursor area) is displayed. these bits should not be cleared to 0. this field is used for both cursor 1 and cursor 2. display shape switching is performed simultaneously for both cursors. 6. cursor blink shape b display interval length (blnkb) these bits set, in field units, the length of the interval during which cursor shape b (stored in the cursor area) is displayed. these bits should not be cleared to 0. this field is used for both cursor 1 and cursor 2. display shape switching is performed simultaneously for both cursors. the cursor is 32 32 pixels in size, and is displayed in the color assigned in the color palette register. set the start positions so that the upper-left coordinates of the cursor display area do not extend outside the frame buffer display screen. also set the start positions so that cursors 1 and 2 do not overlap, as cursor 1 will have priority and cursor 2 will be lost in this case. unlike the hds and vds f ields in the display window registers (dswr), the screen coordinate upper-left reference values should be set in the hcs and vcs fields. in the horizontal direction the upper-left point is 0, and the right direction is positive, with changes made one by one in dot units. in the vertical direction the upper-left point is 0, and the downward direction is positive, with changes made one by one in line units. rev. 2.0, 09/02, page 254 of 366 in cursor blinking, in the cursor display a interval, the 1024 bytes of data from the address specified by the cursor area start address register are used for display. in the cursor display b interval, the 1024 bytes of data from the location obtained by adding 1024 bytes to the address specified by the cursor area start address register are used for display. write 0 to bits that are not used for the hcs1, vcs1, hcs2, vcs2, bli nka, and blinkb fields (a read will return an undefined value). the hcs1, vcs1, hcs2, vcs2, blinka, and blinkb bits in the csr registers r etain their values in a reset. register address: h'074 bit bit name initial value r/w description 15 to 10 ? * r/w blnka 9 to 0 ? * r/w hcs1 register address: h'076 bit bit name initial value r/w description 15 to 10 ?? r/w blnkb 9 ??? 8 to 0 ? * r/w vcs1 register address: h'078 bit bit name initial value r/w description 15 to 9 ?? r/w 8 to 0 ? * r/w hcs2 register address: h'07a bit bit name initial value r/w description 15 to 9 ?? r/w 8 to 0 ? * r/w vcs2 note: * value is retained. rev. 2.0, 09/02, page 255 of 366 5.4.12 color palette registers (cp000r to cp255r) the color palette is mapped onto addresses (a10 to a1) h'200 to h'5fe. settings can be made for 256 colors, with 6 bits each for r, g, and b. the color palette can only be used in 8-bit/pixel mode. when the color palette is accessed by the cpu, bits gbm2 to gbm0 in the rendering mode register (remr) should be set to 000, 010, 100, or 110. in the q2sd, the color palette set values are retained regardless of the gbm values. cp000r register address: h'200 bit bit name initial value r/w description 15 to 8 ??? 7 to 2 ? * r/w r000 (red: 6 bits) 1, 0 ??? register address: h'202 bit bit name initial value r/w description 15 to 10 ? * r/w g000 (green: 6 bits) 9, 8 ??? 7 to 2 ? * r/w b000 (blue: 6 bits) 1, 0 ??? rev. 2.0, 09/02, page 256 of 366 cp001r register address: h'204 bit bit name initial value r/w description 15 to 8 ??? 7 to 2 ? * r/w r001 (red: 6 bits) 1, 0 ??? register address: h'206 bit bit name initial value r/w description 15 to 10 ? * r/w g001 (green: 6 bits) 9, 8 ??? 7 to 2 ? * r/w b001 (blue: 6 bits) 1, 0 ??? cp002r : cp255r register address: h'5fc bit bit name initial value r/w description 15 to 8 ??? 7 to 2 ? * r/w r255 (red: 6 bits) 1, 0 ??? register address: h'5fe bit bit name initial value r/w description 15 to 10 ? * r/w g255 (green: 6 bits) 9, 8 ??? 7 to 2 ? * r/w b255 (blue: 6 bits) 1, 0 ??? note: * value is retained. rev. 2.0, 09/02, page 257 of 366 5.5 rendering control registers the rendering control registers are 16-bit registers, mapped onto addresses (a10 to a1) h'03e to h'040, h080 to h096, and h09a. before the current pointer register (curr), local offset register (lcor), user clipping area register (ulcr), system clipping area register (sclr), or return address register (rtnr) is read, the rbrk of the system control register ( sysr) must be set to 1, and brk must be 1. when these values are read when brk is not 1, an invalid value may be read. command status registers (cstr) current pointer registers (curr) local offset registers (lcor) user clipping area registers (uclr) system clipping area registers (sclr) return address registers (rtnr) 5.5.1 command status registers (cstr) the command status registers (cstr) store the address of the command word (op code word) being executed when a frame change is performed. the upper bits (a22 to a16) of the command word address are indicated by the csth field, and the lower bits (a15 to a1) by the cstl field. the address indicated by the csth and cstl fields is a word address. bits that are not used for the csth and cstl fields are always read as 0. the csth and cstl fields in the cstr registers retain their values in a reset. register address: h'03e bit bit name initial value r/w description 15 to 7 ??? 9 to 0 ? * r csth (address a22 to a16 setting) rev. 2.0, 09/02, page 258 of 366 register address: h'040 bit bit name initial value r/w description 15 to 1 ? * r cstl (address a15 to a1 setting) 0 ??? note: * value is retained. 5.5.2 current pointer registers ( curr) the current pointer registers (curr) indicate the current pointer coordinates. when these registers are read, bits that are not used for the xc and yc fields are always read as 0. the xc and yc bits in the curr registers retain their values in a reset. register address: h'080 bit bit name initial value r/w description 15, 14 ??? 13 ? * rsign 12 to 0 ? * rxc register address: h'082 bit bit name initial value r/w description 15, 14 ??? 13 ? * rsign 12 to 0 ? * ryc note: * value is retained. rev. 2.0, 09/02, page 259 of 366 5.5.3 local offset registers (lcor) the local offset registers (lcor) indicate the offset coordinates. when these registers are read, bits that are not used for the xo and yo fields are always read as 0. the xo and yo bits in the lcor registers retain their values in a reset. register address: h'084 bit bit name initial value r/w description 15, 14 ??? 13 ? * rsign 12 to 0 ? * rxo register address: h'086 bit bit name initial value r/w description 15, 14 ??? 13 ? * rsign 12 to 0 ? * ryo note: * value is retained. 5.5.4 user clipping area registers (uclr) the user clipping area registers (uclr) indicate the user clipping area. when these registers are read, bits that are not used for the uxmin, uymin, uxmax, and uymax f ields are always read as 0. the uxmin, uymin, uxmax, and uymax bits in the uclr registers r etain their values in a reset. rev. 2.0, 09/02, page 260 of 366 register address: h'088 bit bit name initial value r/w description 15, 14 ??? 13 ? * rsign 12 to 0 ? * r uxmin (upper-left x) register address: h'08a bit bit name initial value r/w description 15, 14 ??? 13 ? * rsign 12 to 0 ? * r uymin (upper-left y) register address: h'08c bit bit name initial value r/w description 15, 14 ??? 13 ? * rsign 12 to 0 ? * r uxmax (upper-left x) register address: h'08e bit bit name initial value r/w description 15, 14 ??? 13 ? * rsign 12 to 0 ? * r uymax (upper-left y) note: * value is retained. rev. 2.0, 09/02, page 261 of 366 5.5.5 system clipping area registers (sclr) the system clipping area registers (scl) indicate the system clipping area. when these registers are read, bits that are not used for the sxmax, and symax f ields are always read as 0. the sxmax and symax bits in the sclr registers r etain their values in a reset. register address: h'090 bit bit name initial value r/w description 15, 14 ??? 13 ? * rsign 12 to 0 ? * r sxmax (uppe r-right x) register address: h'092 bit bit name initial value r/w description 15, 14 ??? 13 ? * rsign 12 to 0 ? * r symax (uppe r-right y) note: * value is retained. 5.5.6 return address registers (rtnr) the return address registers (rtnr) specify the return address. the upper bits (a22 to a16) of the start address are set in the rtnh field, and the lower bits (a15 to a1) in the rtnl field. the address (bits a22 to a1) indicated by the rtnh and rtnl fields is a word address. write 0 to bits that are not used for the rtnh and rtnl fields (a read will return an undefined value). the rtnh and rtnl fields in the rtnr registers retain their values in a reset. rev. 2.0, 09/02, page 262 of 366 register address: h'094 bit bit name initial value r/w description 15 to 7 ??? 6 to 0 ? * r/w rtnh (address a22 to a16 setting) register address: h'096 bit bit name initial value r/w description 15 to 1 ? * r rtnl (address a15 to a1 setting) 0 ??? note: * value is retained. 5.5.7 color offset register (color) the offset components are treated as signed integers. this register can be used by the polygon4a co mmand. in 16-bit/pixel drawing, if the rendering attribute c oof bit is set to 1, the result of adding the value in the color register to the value of the multi-valued source data is drawn. the operation is performed by saturation processing. in 8-bit/pixel drawing, the rendering attribute c oof bit must be cleared to 0. register address: h'09a bit bit name initial value r/w description 15 ? * r/w 14 to 11 ? * r/w sign coofr (color offset r) color offset red component 10 ? * r/w 9 to 5 ? * r/w sign coofg (color offset g) color offset green component 4 ? * r/w 3 to 0 ? * r/w sign coofb (color offset b) color offset blue component note: * value is retained. rev. 2.0, 09/02, page 263 of 366 5.6 data transfer control registers the data transfer control registers are related to the control of input data transfer and conversion, mapped onto addresses (a10 to a1) h'020 to h'024 and h'042 to h'04a. 5.6.1 dma transfer start address registers (dmasr) the dma transfer start address registers (dmasr) sp ecify the start address of the transfer destination ugm in a dma transfer. the upper bits (a22 to a16) of the start address are set in the dmash f ield in dmasr, and the lower bits (a15 to a1) in the dmasl f ield in dmasr. if the value of these registers is modified during a series of dma oper ations from the time bits dma1 and dma0 in the sys tem control register ( sysr) are set to 01 by the cpu until they are cleared automatically by the q2sd, operation will be unstable. when bits dma1 and dma0 are set to 11, the value in these registers is not referenced. transfer data passes via the image data entry register (ider), is converted, and stored sequentially starting at the data transfer start address indicated by the image data transfer start address register (isar). the address (a22 to a1) indicated by the dmash and dmasl f ields is a word address. write 0 to bits that are not used for the dmash and dmasl f ields (a read will return an undefined value). the values of the dmash and dmasl f ields in the dmasr registers are in itialized to all-0 by a reset. these registers are not incremented when dma transfer is performed. register address: h'020 bit bit name initial value r/w description 15 to 7 ??? 6 to 0 ? all 0 r/w dmash (address a22 to a16 setting) rev. 2.0, 09/02, page 264 of 366 register address: h'022 bit bit name initial value r/w description 15 to 1 ? all 0 r/w dmash (address a15 to a1 setting) 0 ??? 5.6.2 dma transfer word count registers (dmawr) the dma transfer word count registers (dmawr) sp ecify the number of words (1 word = 16 bits) to be transferred in dma transfer. if the value of these registers is modified during a series of dma oper ations from the time bits dma1 and dma0 in the sys tem control register ( sysr) are set to 01 or 11 by the cpu until they are cleared automatically by the q2sd, operation will be unstable. when bits dma1 and dma0 are set to 11, the value in these registers is not referenced. transfer data passes via the image data entry register (ider), is converted, and stored sequentially starting at the data transfer start address indicated by the image data transfer start address register (isar). write 0 to bits that are not used for the dmawh and dmawl f ields (a read will return an undefined value). the values of the dmawh and dmawl f ields in the dmawr registers are in itialized to all-0 by a reset. these registers are not decremented when dma transfer is performed. register address: h'050 bit bit name initial value r/w description 15 to 3 ??? 2 to 0 ? all 0 r/w dmawh register address: h'054 bit bit name initial value r/w description 15 to 0 ? all 0 r/w dmawl rev. 2.0, 09/02, page 265 of 366 5.6.3 image data transfer start address registers (isar) the image data transfer start address registers (isar) specify the image data transfer destination as a physical address when the setting of bits yuv2, yuv1, and yuv0 is 001, 010, 011, or 111. the upper bits (a22 to a16) of the start address are set in the isah f ield, and the lower bits (a15 to a1) in the isal field. the address indicated by the i sah and isal f ields is a word address. if the value of these registers is modified during a series of data conversion operations from the time bits yuv2, yuv1, and yuv0 are set to 001, 010, 011, or 111 by the cpu un til yuv mode is cleared automatically by the q2sd, operation will be unstable. write 0 to bits that are not used for the i sah and isal f ields. the values of the isah and isal f ields in the isar registers are initialized to all-0 by a reset. these registers are not incremented when image data is transferred. register address: h'042 bit bit name initial value r/w description 15 to 7 ??? 6 to 0 ? all 0 r/w isah (address a22 to a16 setting) register address: h'044 bit bit name initial value r/w description 15 to 1 ? all 0 r/w isal (address a15 to a1 setting) 0 ??? rev. 2.0, 09/02, page 266 of 366 5.6.4 image data size registers ( idsr) the image data size registers (idsr) specify the image data x size and y size when the setting of bits yuv2, yuv1, and yuv0 is 001, 010, 011, or 111. for the image data x size, set the number of pixels when bits yuv2, yuv1, and yuv0 = 001, 010, or 011, and set 1/2 the number of pixels when bits yuv2, yuv1, and yuv0 = 111. an even number should be set for the x size (i dsx0 bit = 0). if the value of these registers is modified during a series of data conversion operations from the time bits yuv2, yuv1, and yuv0 are set to 001, 010, 011, or 111 by the cpu un til yuv mode is cleared automatically by the q2sd, operation will be unstable. write 0 to bits that are not used for the i dsx and idsy f ields. the values of the idsx and idsy bits in the idsr registers are in itialized to all-0 by a reset. register address: h'046 bit bit name initial value r/w description 15 to 11 ??? 10 to 0 ? all 0 r/w idsx * register address: h'048 bit bit name initial value r/w description 15 to 10 ??? 9 to 0 ? all 0 r/w idsy rev. 2.0, 09/02, page 267 of 366 5.6.5 image data entry register (ider) the image data entry register (ider) comprises the entry in which image data is input when the setting of bits yuv2, yuv1, and yuv0 is 001, 010, 011, or 111. the ider is initialized to h'0000 by a reset. register address: h'048 bit bit name initial value r/w description 15 to 0 ? all 0 w ide rev. 2.0, 09/02, page 268 of 366 rev. 2.0, 09/02, page 269 of 366 section 6 usage notes 6.1 power-on sequence the timing of the clk0, clk1, and reset signals at power-on is shown in figure 6.1. set 50 ms or less as the time from the rising edge of vccn to the rising edge of clk0/clk1, and 100 ms or more as the time from the rising edge of vccn to the rising edge of reset. if clk0 and clk1 are halted for a long time (50 ms or more) after powering on, the device may be permanently damaged. vcc clk0, clk1 vcc min v ihc v ilt v ilt min. 100 ms less than 50 ms figure 6.1 power-on sequence rev. 2.0, 09/02, page 270 of 366 6.2 use of 64-mbit sdram ( 16 type) the q2sd references the value of bits mes1 and mes0 in the memory mode register (mmr) following the elapse of 70 tcyc0 after a hardware reset, and makes the udqm1 pin the ma13 signal output pin if mes1 and mes0 = b 10, or the upper word upper byte input/output mask signal output pin if mes1 and mes0 = b 00. if the setting of mes1 and mes0 has not been carried out by this time, the values of mes1 and mes0 cleared by a hardware reset will be referenced. therefore, only when using the mes1 and mes0 = 1, 0 mode (64-mbit ( 16) memory size, one memory used, 16-bit bus), the mes1, mes0 = 1, 0 setting must be made before the elapse of 70 tcyc0 after a hardware reset. rev. 2.0, 09/02, page 271 of 366 6.3 cpu interface unit fifo the q2sd stores the display list which is sent from the cpu to the ugm via a 16-word on-chip fifo. the cpu gives the rendering start instruction to the q2sd after the transfer of display list. however, note that when the rendering start address is within the last 16-word data at the end of the display list, the q2sd may fetch the previous fetch-starting data on the ugm before the completion of flushing the fifo caused by the start of rendering. to avoid the such previous data from being fetched, cpu must perform ugm dummy read after the display list transfer, and give instruction to start rendering to the q2sd. rendering start bit (rs) when rs is set to 1, starts fetching the data (display list) on the ugm from the address that is shown by the display list start address register (dlasr). display list start address register (dlsar) register that stores the display list fetching start address. rev. 2.0, 09/02, page 272 of 366 6.4 video fetching start timing data is captured at the timing of detecting two rising edges of the vhs signal after d etecting vvs = 1 and vhs = 1. the vqclk must be input only for n ecessary data. 1h line period vhs high period video data is not incorporated. vqclk is ignored. video data is incorporated. details: vqclk vin ab t vhs t vos figure 6.2 video interface timing 6.5 drawing using linear format source when the polygon4a, polygon4b, pline, or rplinr co mmand is executed with linear format source specified, there is the following restriction regarding the size in the x direction of the linear format source. if a command is executed ignoring the restriction, the error drawing (dot) absence may occur. use the above commands within the following restrictions. rev. 2.0, 09/02, page 273 of 366 source x direction maximum size marking specifications 1 bit/pixel 8 bits/pixel 16 bits/pixel product type marking type no. mask code byte tdx (pixel) byte tdx (pixel) byte tdx (pixel) hd64413af hd64413af none 1 to 32 8 to 256 8 to 32 8 to 32 16 to 32 8 to 16 hd64413afi hd64413afi none 1 to 32 8 to 256 8 to 32 8 to 32 16 to 32 8 to 16 hd64413asf hd64413af s 1 to about 128 8 to 1023 8 to 1023 8 to 1023 8 to 1023 8 to 1023 hd64413asfi hd64413afi s 1 to about 128 8 to 1023 8 to 1023 8 to 1023 8 to 1023 8 to 1023 note: tdx: source x direction size (pixel) products with restrictions: hd64413af, hd64413afi products with no restrictions: hd64413asf, hd64413asfi 6.6 sdram mode register values for ugm set by q2sd initial sequence is executed in order to set the mode register in the sdram which is connected as the ugm that is set by the q2sd. the sdram that is used for the ugm must support the following functions that are set by the q2sd. the mode register settings in the sdram are the following fixed values. please keep in mind that those values depend on mask version of the q2sd. rev. 2.0, 09/02, page 274 of 366 type no. marking no. process code mask code sdram operating mode set by the q2sd hd64413af* 4 hd64413af none none burst read & burst write mode, cas latency ? 3, burst type is sequential, burst length ? 1* 1 hd64413af* 4 hd64413af i none burst read & burst write mode, cas latency ? 3, burst type is sequential, burst length ? 1* 1 hd64413asf hd64413af none s burst read & single write mode, cas latency ? 3, burst type is sequential, burst length ? 1* 2 * 3 hd64413asfi hd64413af i s burst read & single write mode, cas latency ? 3, burst type is sequential, burst length ? 1* 2 * 3 notes: 1. sdram mode register value set by the q2sd is h2030. when a single sram with the memory capacity of 64 mbits and data width of 16 bits is used, select a product which the sram mode register bit that corresponds to q2sd ma13 is dont care. 2. sdram mode register value set by the q2sd is h2230. when a single sram with the memory capacity of 64 mbits and data width of 16 bits is used, select a product which the sram mode register bit that corresponds to q2sd ma13 is dont care. 3. normal operation can be performed by the following sdram even though they do not support the burst read & single write mode: msm56v16160f (oki electric industry co., ltd., 2-bank x 512-kword x 16-bit sdram f version) 4. the production of the hd64413af and the hd64413afi will be discontinued after the hd64413asf and the hd64413asfi start mass production. rev. 2.0, 09/02, page 275 of 366 section 7 electrical characteristics 7.1 absolute maximum ratings table 7.1 absolute maximum ratings item symbol value unit power supply voltage v cc * 1 C0.3 to +4.6 v input voltage v in * 1 C0.3 to v cc +0.3 v permissible output low current | i ol | * 2 2ma total permissible output low current | s i ol | * 3 172 ma permissible output high current | Ci oh | * 2 2ma total permissible output high current | s (Ci oh ) | * 3 172 ma operating temperature t opr 0 to 70 c storage temperature t stg C55 to +125 c notes: 1. value based on gnd = 0 v. includes dav cc and pllv cc . 2. the permissible output current is the maximum value of the current drawn in or flowing out from one output pin and one input/output pin. 3. the total permissible output current is the sum of currents drawn in or flowing out from output pins and input/output pins. caution: permanent damage to the chip may result if absolute maximum ratings are exceeded. in normal operation, it is advisable to observe the recommended operating conditions. exceeding these conditions may adversely affect the reliability of the chip. 7.2 recommended operating conditions table 7.2 recommended operating conditions item symbol min typ max unit power supply voltage v cc * 1 3.0 3.3 3.6 v input low voltage (except clk0, clk1) v ilt * 1 0 ? 0.6 v input low voltage (clk0, clk1) v ilc * 1 0 ? 0.6 v input high voltage (except clk0, clk1) v iht * 1 2.2 ? v cc v input high voltage (clk0, clk1) v ihc * 1 0.8v cc ? v cc v operating temperature t opr * 2 0 2570c notes: 1. value based on gnd = 0 v. 2. for details on the product with the operating temperature of -40 c to 85 c, please contact your hitachi sales agency. rev. 2.0, 09/02, page 276 of 366 7.3 electrical characteristics test methods 7.3.1 timing testing the output low voltage for timing testing is 1.5 v. the output high voltage for timing testing is 1.5 v. v oh v 0 t reference point v ol for timing testing dc level (steady) v ol figure 7.1 basis of v ol timing testing rev. 2.0, 09/02, page 277 of 366 7.3.2 test load circuit (all output and input/output pins) test point c r rl v input/output timing test levels (excluding clk0 and clk1) low level: 1.5 v high level: 1.5 v v = 3.3 v rl = 2 k w c = 60 pf r = 11 k w all diodes are hitachi 1s2074 equivalent products. figure 7.2 test load circuit rev. 2.0, 09/02, page 278 of 366 7.4 electrical characteristics 7.4.1 dc characteristics table 7.3 dc characteristics unless otherwise indicated, v cc = dacv cc = pllv cc = 3.3 v 0.3 v, gnd = dacgnd = pllgnd = 0 v, t a = 0 to +70c. each value listed below is target one. some values are reflected the result of the test of sample chips. item pin names symbol min max unit test conditions input high voltage (cmos level) i1 v ihc 0.8 v cc v cc + 0.3 v input low voltage (cmos level) v ilc C0.3 v cc 0.2 input high voltage (ttl level) i2, io v iht 2.2 v cc + 0.3 v input low voltage (ttl level) v ilt C0.3 v cc 0.2 input leakage current i1, i2 i in ? 1 m av in = 0 C v cc three-state leakage current (off state) io, o i tsi ? 1v in = 0.4 C v cc output high voltage io, o v oh 2.2 ? vi oh = C200 m a output low voltage io, o v ol ? 0.6 i ol = 1.6 ma input capacitance io c in ? 20 pf v in = 0 v i1, i2 ? 20 t a = 25c f = 1.0 mhz current consumption i cc ? 350 ma data bus operating/display operating/ command being executed note: the symbols used in table 7.3 are explained below. rev. 2.0, 09/02, page 279 of 366 symbol input output high-z pull-up pin names i1 cmos ??? clk0, clk1 i2 ttl ??? mod2 to mod0, 5(6(7 , a22 to a1, &6 , &6 , 5' , :( , :( , '$&. , vin7 to vin0, 9+6 996 , 92'' , vqclk io ttl cmos yes ? d15 to d0, +6<1& / (;+6<1& , 96<1& / (;96<1& , 2'') , md31 to md0 o ? cmos ?? '5(4 , :$,7 , ,5/ , &6<1& , disp, cde, ma13 to ma0, 0&6 , 0:( , 05$6 , 0&$6 , ldqm1, ldqm0, udqm1, udqm0, mclk rev. 2.0, 09/02, page 280 of 366 7.4.2 ac characteristics clocks table 7.4 input clocks (pins mode2 to mode0 = 000, 001, or 010: multip lication on) unless otherwise indicated, v cc = dacv cc = pllv cc = 3.3 v 0.3 v, gnd = dacgnd = pllgnd = 0 v, t a = 0 to +70c. each value listed below is target one. some values are reflected the result of the test of sample chips. item symbol min max unit test conditions notes clk0 cycle time 1 t cyc 15 25 ns figure 7.3 1 clk0 cycle time 2 t cyc 30 50 ns 2 clk0 cycle time 3 t cyc 60 100 ns 4 clk0 high pulse width t cpwh 5.5 ? ns clk0 low pulse width t cpwl 5.5 ? ns mclk cycle time t cyc0 15 25 ns mclk high pulse width t cmpwh 5.0 ? ns mclk low pulse width t cmpwl 5.0 ? ns clk1 cycle time t cyc1 30 200 ns clk1 high pulse width t c1pwh 10 ? ns clk1 low pulse width t c1pwl 10 ? ns clk1 duty t c1dt 0.5t cyc1 C 0.07t cyc1 0.5t cyc1 + 0.07t cyc1 ns clk1 rise time t cr ? 5.0 ns clk1 fall time t cf ? 5.0 ns mclk rise time t mcr ? 4.5 ns mclk fall time t mcf ? 4.5 ns reset table 7.5 reset item symbol min max unit test conditions notes 5(6(7 low pulse width t resw 40 ? t cyc0 figure 7.4 rev. 2.0, 09/02, page 281 of 366 cpu read cycle table 7.6 cpu read cycle item symbol min max unit test conditions notes address setup time t ads 0 ? ns figure 7.5 address hold time t adh 0 ? ns 1 &6q setup time t css 0 ? ns 2 &6q hold time t csh 0 ? ns 3 :$,7 cycle start time 1 t was1 ? 3t cyc0 + 15 ns 5' high width t rdhw t cyc0 ? ns read data setup time with respect to :$,7 t rddws 0 ? ns :$,7 drive time t wad t cyc0 ? ns read data turn-on time t rddon 0 ? ns read data hold time t rddh 1.5 ? ns read data turn-off time t rddof 1.5 ? ns :( high width t wehw t cyc0 ? ns notes: 1. address signals a22 to a1 must be held at least until the rise of :$,7 . 2. if the fall of &6q is later than the fall of 5' , the specifications for t ads , t was1 , t rddon , and t wehw are from the fall of &6q . &6q = &6 , &6 . 3. if the rise of &6q is earlier than the rise of 5' , the specifications for t adh , t rddh , t rddof , and t wehw are from the rise of &6q . &6q = &6 , &6 . rev. 2.0, 09/02, page 282 of 366 cpu write cycle table 7.7 cpu write cycle item symbol min max unit test conditions notes address setup time t ads 0 ? ns figure 7.6 address hold time t adh 2 ? ns &6q setup time t css 0 ? ns 1 &6q hold time t csh 0 ? ns 2 5' high width t rdhw t cyc0 ? ns :$,7 drive time t wad t cyc0 ? ns :$,7 cycle start time 2 t was2 ? 3t cyc0 + 15 ns :( high width t wehw t cyc0 ? ns 3 write data setup time with respect to :( t wrdes 2t cyc0 ? ns 3 write data hold time t wrdh 2 ? ns notes: 1. if the fall of &6q is later than the fall of :(q , the specifications for t ads , t rdhw , and t was2 are from the fall of &6q . &6q = &6 , &6 ; :(q = :( , :( . 2. if the rise of &6q is earlier than the rise of :(q , the specifications for t adh , t rdhw , t wrdes , t wrdh , and t wrdof are from the rise of &6q . &6q = &6 , &6 ; :(q = :( , :( . 3. :(q = :( , :( . rev. 2.0, 09/02, page 283 of 366 dma write cycle table 7.8 dma write cycle item symbol min max unit test conditions notes 5' high width t rdhw t cyc0 ? ns figure 7.7 (1), 5' low width t rdlw 3t cyc0 ? ns (2), (3), (4) :( high width t wehw t cyc0 ? ns write data hold time t wrdh 2 ? ns write data setup time with respect to 5' t wrdrs 2t cyc0 ? ns '5(4 negate time with respect to 5' t darn ? 3t cyc0 + 15 ns '5(4 assert time with respect to 5' t dara 3t cyc0 + 15 ? ns '$&. setup time with respect to 5' t dars 0 ? ns '$&. hold time with respect to 5' t darh 0 ? ns '$&. setup time with respect to :( t daws 0 ? ns '$&. hold time with respect to :( t dawh 0 ? ns :( low width t welw 3t cyc0 ? ns write data setup time with respect to :( t wrdws 2t cyc0 ? ns write data hold time with respect to :( t wrdwh 2 ? ns '5(4 negate time with respect to :( t dawn ? 3t cyc0 + 15 ns '5(4 hold time with respect to :( t dawa 3t cyc0 + 15 ? ns notes: 1. if the fall of '$&. is later than the fall of 5' , the specification for t rdlw is from the fall of '$&. . 2. if the rise of '$&. is earlier than the rise of 5' , the specifications for t rdlw , t wrdh , and t wrdrs are from the rise of '$&. . 3. if the fall of '$&. is later than the fall of :(q , the specification for t welw is from the fall of '$&. . :(q = :( , :( . 4. if the rise of '$&. is earlier than the rise of :(q , the specifications for t welw , t wrdws , and t wrdwh are from the rise of '$&. . :(q = :( , :( . rev. 2.0, 09/02, page 284 of 366 interrupt output table 7.9 interrupt output item symbol min max unit test conditions notes ,5/ delay time t ird ? 15 ns figure 7.8 ugm read cycle table 7.10 ugm read cycle item symbol min max unit test conditions notes md input setup time t mdis 6 ? ns figure 7.9 md input hold time t mdih 3 ? ns md input turn-on time t mdin 0 ? ns md input turn-off time t mdif ? 9ns ma delay time t mad ? 12 ns ma hold time t mah 1 ? ns md output turn-off time t mdof ? 12 ns md output turn-on time t mdon 0 ? ns mcs delay time t mcsd ? 12 ns mcs hold time t mcsh 1 ? ns ugm write cycle table 7.11 ugm write cycle item symbol min max unit test conditions notes md output delay time t mdod ? 12 ns figure 7.10 md output hold time t modh 1 ? ns ma delay time t mad ? 12 ns ma hold time t mah 1 ? ns mcs delay time t mcsd ? 12 ns mcs hold time t mcsh 1 ? ns rev. 2.0, 09/02, page 285 of 366 ugm refresh cycle/mode register setting cycle table 7.12 ugm refresh cycle/mode register setting cycle item symbol min max unit test conditions notes ma delay time t mad ? 12 ns figure 7.11 ma hold time t mah 1 ? ns (1), (2) mcs delay time t mcsd ? 12 ns mcs hold time t mcsh 1 ? ns master display mode table 7.13 master display mode item symbol min max unit test conditions notes +6<1& delay time from clk1 t hsdd ? 15 ns figure 7.12 96<1& delay time from clk1 t vsdd ? 15 ns 2'') delay time from clk1 t oddd ? 15 ns &6<1& delay time from clk1 t sydd ? 15 ns disp delay time from clk1 t didd ? 15 ns cde delay time from clk1 t cdedd ? 15 ns rev. 2.0, 09/02, page 286 of 366 tv sync display mode table 7.14 tv sync display mode item symbol min max unit test conditions notes disp delay time from clk1 t didd ? 15 ns figure 7.13 cde delay time from clk1 t cdedd ? 15 ns (1), (2) (;+6<1& low width t exllw 4t cyc1 ? ns (;+6<1& high width t exhhw 4t cyc1 ? ns (;+6<1& reception undefined time 1 t exh1 5 ? ns (;+6<1& reception undefined time 2 t exh2 5 ? ns disp start time with respect to (;+6<1& t diexh hds C 1 hds C 1 t cyc1 * (;96<1& low width t exvlw 3hc ? t cyc1 (;96<1& reception undefined time 1 t exv1 5 ? ns (;96<1& reception undefined time 2 t exv2 5 ? ns 2'') reception undefined time 1 t od1 (ys + yw) hc ? t cyc1 2'') reception undefined time 2 t od2 1t cyc1 ? ns note: * hds = hsw + xs rev. 2.0, 09/02, page 287 of 366 video interface table 7.15 video interface item symbol min max unit test conditions notes vqclk high pulse width t qhw 15 ? ns figure 7.14 vqclk low pulse width t qlw 15 ? ns (1), (2) 92'' setup time t vos 1 ? t cyc0 vin setup time t vns 5 ? ns vin hold time t vnh 11.7 ? ns 996 low pulse width t vvl 2 ? hline * 9+6 low pulse width t vhl 64 ? t cyc0 vqclk risevqclk rise interval t qqp 34.5 ? ns t qqp > 2 t cyc0 92'' hold time t voh 1 ? t cyc0 996 setup time t vhs 5 ? t cyc0 9+6 setup time t hqs 10 ? t cyc0 9+6 reception undefined time t vhsru 2 ? hline * note: * hline is the 9+6 cycle. video dac table 7.16 video dac item symbol min max unit test conditions notes resolution 8 8 bit dc test differential linearity error ? 0.5 lsb dc test conversion speed ? 33 mhz data write test maximum output current i out 3ma analog full-scale output 0.9 1.1 v dc test analog zero-scale output C0.1 0.1 v dc test full-scale error C10 10 % dc test rev. 2.0, 09/02, page 288 of 366 7.5 timing charts 7.5.1 clocks v oh t cyc0 t cyc1 t cmpwh t cmpwl t m cr t m cf t cr t cf v oh 0.5v cc v oh 0.5v cc v oh v oh 0.5v cc v oh v ih 0.5v cc v il t c1pwh t c1pwl v ih 0.5v cc v il t c1dt t c1dt v ih 0.5v cc v il t cyc t cpwh t cpwl v ih 0.5v cc v ih 0.5v cc v il 0.5v cc v il clk0 (input) (pins mode2 to mode0 = 000) mclk (output) (pins mode2 to mode0 = 000, 001, 010) clk1 (input) (pins mode2 to mode0 = 000, 001, 010) figure 7.3 input clocks 7.5.2 reset timing (input) t resw figure 7.4 reset timing rev. 2.0, 09/02, page 289 of 366 7.5.3 cpu read cycle timing a22 to a1 (input) to (input) (input) to (input) (output) d15 to d0 (input/output) (input) t adh t ads t css t csh t was1 t rdhw t wad t rddon high (cannot be low simultaneously with / ) t wehw t wehw t rddh t rddof t rddws t rdhw figure 7.5 cpu read cycle timing (cpu ? q2sd) with hardware wait rev. 2.0, 09/02, page 290 of 366 7.5.4 cpu write cycle timing t csh t adh t css t ads t rdhw t was2 t wad t wrdes t wehw t rdhw t wehw t wrdh a22 to a1 (input) to (input) (input) to (input) (output) d15 to d0 (input/output) (input) high (cannot be low simultaneously with / ) figure 7.6 cpu read cycle timing (cpu ? q2sd) with hardware wait rev. 2.0, 09/02, page 291 of 366 7.5.5 dma write cycle timing (dmac ? q2sd) t wrdrs t wrdh to (input) (input) (output) d15 to d0 (input/output) (dda1 = 0, dda0 = 1) t rdhw t rdhw t rdlw t darh t dars (input) to (input) high t wrdrs t wrdh d15 to 0 (input/output) (dda1 = 0, dda0 = 1) high (cannot be low simultaneously with ) high (cannot be low simultaneously with ) figure 7.7 (1) dma write cycle timing (single address, dmac ? q2sd) rev. 2.0, 09/02, page 292 of 366 (input) t rdhw t darn t darh (input) to (output) t dara high (cannot be low simultaneously with ) t dars figure 7.7 (2) dma write cycle timing (single address, dmac ? q2sd) rev. 2.0, 09/02, page 293 of 366 t wrdws t wrdwh (input) (input) (output) d15 to d0 (input/output) t wehw t wehw t welw t dawh t daws (input) to (input) high high (cannot be low simultaneously with / ) figure 7.7 (3) dma write cycle timing (dual address, dmac ? q2sd) rev. 2.0, 09/02, page 294 of 366 (input) t wehw t dawn t dawh (input) to (input) (output) t dawa t daws high (cannot be low simultaneously with / ) figure 7.7 (4) dma write cycle timing (dual address, dmac ? q2sd) rev. 2.0, 09/02, page 295 of 366 7.5.6 interrupt output timing mclk (output) t ird t ird figure 7.8 interrupt output timing rev. 2.0, 09/02, page 296 of 366 7.5.7 ugm read cycle timing # ! " ! ! mclk (output) (output) (output) (output) ma11 (output) ma10 (output) ma9 (output) ma8 (output) ma7 to ma0 (output) ldqm0, ldqm1, udqm0, udqm1 (output) md31 to md0 (input/output) t mcsd t mcsd t mcsd t mcsd t mcsd t mad t mah t mcsh t mcsh t mcsh t mcsh t mcsd t mcsd t mcsh t mdof t mdis t mdih t mdon t mdif t mdin t mcsd t mcsd t mcsd t mcsd t mcsd t mcsh t mcsh t mcsh t mcsh t mcsh t mcsh t mcsh figure 7.9 ugm read cycle timing rev. 2.0, 09/02, page 297 of 366 7.5.8 ugm write cycle timing # ! " ! ! ! mclk (output) (output) (output) (output) ma11 (output) ma10 (output) ma9 (output) ma8 (output) ma7 to ma0 (output) ldqm0, ldqm1, udqm0, udqm1 (output) md31 to md0 (input/output) t mcsd t mcsd t mcsd t mcsd t mcsd t mad t mah t mcsh t mcsh t mcsh t mcsh t mcsd t mcsd t mdod t mdoh t mcsh t mcsd t mcsd t mcsd t mcsd t mcsd t mcsh t mcsh t mcsh t mcsh t mcsh t mcsh t mcsd t mcsh t mcsh t mcsh t mcsd figure 7.10 ugm write cycle timing rev. 2.0, 09/02, page 298 of 366 7.5.9 ugm refresh cycle timing and mode register setting timing ! ! ! ! ! mclk (output) (output) (output) (output) ma11 to ma0 (output) ldqm0, ldqm1, udqm0, udqm1 (output) md31 to md0 (input/output) t mcsh t mcsd t mcsh t mcsd t mcsh t mcsd t mcsh t mcsd figure 7.11 (1) ugm refresh cycle timing rev. 2.0, 09/02, page 299 of 366 ! ! ! ! ! ! mclk (output) (output) (output) (output) ma11 to ma0 (output) ldqm0, ldqm1, udqm0, udqm1 (output) md31 to md0 (input/output) t mcsh t mcsd t mcsh t mcsd t mcsh t mcsd ! t mcsh t mcsd t mad t mah figure 7.11 (2) ugm mode register setting cycle timing rev. 2.0, 09/02, page 300 of 366 7.5.10 master mode display timing t1 clk1 (input) r,g,b (output) t1 t1 (output) (output) (output) (output) disp (output) cde (output) t hsdd t hsdd t vsdd t vsdd t oddd t oddd t sydd t sydd t didd t didd t cdedd t cdedd figure 7.12 master mode display timing rev. 2.0, 09/02, page 301 of 366 7.5.11 tv sync mode display timing t1 clk1 (input) r,g,b (output) t1 t1 (output) disp (output) cde (output) high t didd t didd t cdedd t cdedd figure 7.13 (1) tv sync mode display timing rev. 2.0, 09/02, page 302 of 366 1t cyc1 disp (output) r,g,b (output) clk1 (input) (input) (input) (input) clk1 (input) t exhhw t exh2 t exllw t exh1 t exh1 t exv1 t exvlw t od2 t od1 t diexh t exv2 t didd figure 7.13 (2) tv sync mode display timing rev. 2.0, 09/02, page 303 of 366 7.5.12 video interface timing t qqp t qhw t qlw t vns t vnh vqclk vin[7:0] figure 7.14 (1) video interface timing vqlk while or is a low level, or during t vhs and t hqs , or t vhsru , vqclk must not be input. t vvl t vhl t h qs t vhs t vhsru t vos t voh figure 7.14 (2) video interface timing rev. 2.0, 09/02, page 304 of 366 rev. 2.0, 09/02, page 305 of 366 appendix a initial register values table a.1 initial register values after hardware reset ?? ? ? ? dma transfer word count image data transfer start address image data size image data entry dma transfer word count display mode 2 video incorporation mode register address register name abbre- viation system control status status register clear interrupt enable memory mode display mode rendering mode input data conversion mode a [10:0] data only bits marked are affected by a reset. registers other than those shown above are not affected by a reset. dma transfer start address 020 022 024 r/w r/w r/w h h l l dmawr 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w w r/w 042 044 046 048 04a 050 r/w r/w r/w r/w r/w ider dmawr 056 dsmr2 072 vimr h l x y 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 isar idsr 000 1514131211109876543210 000 002 004 006 008 00a 00c 00e r/w r/w r w r/w r/w r/w r/w r/w 1 0 sysr sr srcr ier memr dsmr remr iemr 1514131211109876543210 110 0 0 0 dbm1 dbm0 0 0000000dbf tvcl frcl dmcl cecl vbcl trcl cscl 0000000 0 1100 0 01 0 0 scm1 scm0 mwx gbm1 gbm0 gbm2 01 brcl 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 1 1 0 0 0 0 dmasr 0 0 0 0 0 0 0 0 0 csy1 csy0 rev. 2.0, 09/02, page 306 of 366 appendix b commands and parameters b.1 relationship between commands and rendering attributes table b.1 relationship between commands and rend ering attributes polygon4a polygon4b polygon4c line rline pline rpline ftrap rftrap clrw linew rlinew move rmove lcofs rlcofs clip wpr jump gosub ret nop3 vbkem trap multi-valued source binary source binary work specified color rendering work trns styl clip net eos half work bold line drawing fst lni edg rel coof line drawing edge command reference data drawing destination rendering attributes o: can be used v: can be used (specified color is binary eos bit value) a: referenced depending on mode (valid when work = 1) b: referenced depending on mode (valid when edg = 1) * : referenced depending on mode (clear to 0 when fst = 1) z: referenced depending on mode (clear to 0 when lni = 1) blank: cannot be used (clear to 0) : can be used with restriction, half: x < 0 is prohibited, coof: miniaturization is prohibited.) o o o o a a ao o o v v o o o o o o o o o o o o * o o o * o o o o o o o o o o o o o o o * o * o o o o * o * o o o o b b o o * o * o o o o * o o z o o o o o rev. 2.0, 09/02, page 307 of 366 b.2 command codes table b.2 command codes 15 0 draw mode code command polygon4a polygon4b polygon4c ftrap rftrap linew rlinew line rline pline rpline move rmove lcofs rlcofs clrw uclip sclip jump gosub ret trap 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 code 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 wpr 10110 1 0 1 vbkem 11010 1 1 0 nop3 rev. 2.0, 09/02, page 308 of 366 b.3 command parameter specifications note that words of the command code are omitted. rev. 2.0, 09/02, page 309 of 366 polygon4 commands 15 txs or tys 0 source starting point txs or tys given as unsigned max. 10-bit data. specify correctly according to source area size. 15 source address h 0 1-bit/pixel source start upper address given as upper 10 bits. 15 tdx or tdy 0 source size tdx or tdy given as unsigned max. 10-bit data. tdx can only be set in 8-pixel units. 15 source address l 0 1-bit/pixel source start lower address given as lower 13 bits. source address is set as a byte address. 15 0 source start relative upper address given as upper 10 bits. use sign extension in upper vacant bits. 15 0 source start relative lower address given as lower 13 bits. 15 dxn or dyn sign extension sign extension 0 10 11 12 rendering, work coordinate vertex coordinate dxn or dyn (1 n 4) given as signed 12-bit data. use sign extension in upper vacant bits. 15 color0 0 16-bit/pixel color specification color data 0 given as 16-bit data. 15 color1 or color 0 16-bit/pixel color specification color data 1 given as 16-bit data. 8-bit/pixel color specification color data 0 given as repeated 8-bit data. 15 color0 color0 0 15 color1 or color color1 or color 0 8-bit/pixel color specification color data 1 given as repeated 8-bit data. : fixed at 0 sign sign relative source address h relative source address l rev. 2.0, 09/02, page 310 of 366 ftrap, rftrap 15 0 number of vertices (2 n 65,535), absolute (1 n 65,535), relative given as unsigned 16-bit data. n absolute coordinate vertex coordinate dxn (2 n 65,535) given as signed 12-bit data. use sign extension in upper vacant bits. left-hand side coordinate dxl given as signed 12-bit data. use sign extension in upper vacant bits. 15 0 10 12 11 dxl 15 0 10 12 11 dxn 15 0 10 12 11 dyn absolute coordinate vertex coordinate dyn (2 n 65,535) given as signed 12-bit data. use sign extension in upper vacant bits. 15 dyn dxn 0 relative coordinates vertex coordinates dxn, dyn (1 n 65,535) given as signed 8-bit data. sign extension sign sign sign sign sign sign extension sign extension linew, rlinew absolute coordinate vertex coordinate dxn (2 n 65,535) given as signed 12-bit data. use sign extension in upper vacant bits. absolute coordinate vertex coordinate dyn (2 n 65,535) given as signed 12-bit data. use sign extension in upper vacant bits. 15 dyn dxn 0 relative coordinates vertex coordinates dxn, dyn (1 n 65,535) given as signed 8-bit data. 15 0 number of vertices (2 n 65,535), absolute (1 n 65,535), relative given as unsigned 16-bit data. n 15 0 10 12 11 dxn 15 0 10 12 11 dyn sign extension sign sign extension sign sign sign rev. 2.0, 09/02, page 311 of 366 clrw left and right x coordinates xmin, xmax given as unsigned 12-bit data. upper and lower y coordinates ymin, ymax given as signed 12-bit data. 15 0 10 12 11 11 15 0 10 12 xmin or xmax ymin or ymax sign extension sign sign extension sign line, rline 15 0 number of vertices (2 n 65,535), absolute (1 n 65,535), relative given as unsigned 16-bit data. n 15 line color line color 0 8-bit/pixel color specification color data given as repeated 8-bit data. 15 line color0 0 16-bit/pixel color specification color data given as 16-bit data. absolute coordinate vertex coordinate dxn (2 n 65,535) given as signed 12-bit data. use sign extension in upper vacant bits. absolute coordinate vertex coordinate dyn (2 n 65,535) given as signed 12-bit data. use sign extension in upper vacant bits. 15 dyn dxn 0 relative coordinates vertex coordinates dxn, dyn (1 n 65,535) given as signed 8-bit data. 15 0 10 12 11 dxn 15 0 10 12 11 dyn sign extension sign sign extension sign sign sign rev. 2.0, 09/02, page 312 of 366 pline, rpline 15 line color line color 0 8-bit/pixel color specification color data given as repeated 8-bit data. absolute coordinate vertex coordinate dxn (2 n 65,535) given as signed 12-bit data. use sign extension in upper vacant bits. absolute coordinate vertex coordinate dyn (2 n 65,535) given as signed 12-bit data. use sign extension in upper vacant bits. 15 0 number of vertices (2 n 65,535), absolute (1 n 65,535), relative given as unsigned 16-bit data. n 15 line color0 0 16-bit/pixel color specification color data given as 16-bit data. 15 source address h 0 1-bit/pixel source start upper address given as upper 10 bits. 15 tdx lppt 0 source size tdx line pattern pointer lppt given as unsigned max. 10-bit data. tdx can only be set in 8-pixel units. 15 0 1-bit/pixel source start lower address given as lower 13 bits. source address is set as a byte address. 15 dyn dxn 0 relative coordinates vertex coordinates dxn, dyn (1 n 65,535) given as signed 8-bit data. : fixed at 0 source address l 15 0 10 12 11 dxn 15 0 10 12 11 dyn sign extension sign sign extension sign sign sign rev. 2.0, 09/02, page 313 of 366 move, rmove absolute coordinate vertex coordinate xc given as signed 12-bit data. use sign extension in upper vacant bits. absolute coordinate vertex coordinate yc given as signed 12-bit data. use sign extension in upper vacant bits. 15 yc xc 0 relative coordinates vertex coordinates xc, yc given as signed 8-bit data. 15 0 10 12 11 xc 15 0 10 12 11 yc sign extension sign sign extension sign sign sign lcofs, rlcofs relative specification local offset value xo or yo given as signed 12-bit data. use sign extension in upper vacant bits. 15 yo xo 0 relative specification local offset values xo, yo given as signed 8-bit data. 15 0 10 12 11 xo or yo sign extension sign sign sign uclip, sclip 15 15 : fixed at 0 xmin, xmax 0 left and right x coordinates xmin, xmax given as unsigned 10-bit data. ymin, ymax 0 upper and lower y coordinates ymin, ymax given as unsigned 9-bit data. rev. 2.0, 09/02, page 314 of 366 jump 15 15 : fixed at 0 jump address h 0 jump destination upper address given as upper 10 bits. 0 jump destination lower address given as lower 13 bits. jump destination address is set as an even byte address. jump address l 15 0 relative jump destination upper address given as upper 10 bits. use sign extension in upper vacant bits. 15 0 relative jump destination lower address given as lower 13 bits. jump destination address is set as an even byte address. relative jump address h relative jump address l sign extension sign wpr 15 rn 0 register number rn given as 10-bit data. settable registers are limited. 15 data 0 data given as 16-bit data. : fixed at 0 rev. 2.0, 09/02, page 315 of 366 gosub 15 absolute subroutine address h 0 subroutine upper address given as upper 10 bits. 15 absolute subroutine address l 0 subroutine lower address given as lower 13 bits. subroutine destination address is set as an even byte address. : fixed at 0 15 0 relative subroutine destination upper address given as upper 10 bits. use sign extension in upper vacant bits. 15 0 relative subroutine destination lower address given as lower 13 bits. subroutine destination address is set as an even byte address. relative subroutine address h relative subroutine address l sign extension sign nop3, vbkem 15 dummy 0 cannot be referred. 15 dummy 0 cannot be referred. ret, trap command code words only. no parameters. rev. 2.0, 09/02, page 316 of 366 appendix c drawing algorithms straight line drawing algorithms: 8-point drawing and 4-point drawing figures c.1 (a) and (b) show examples of straight lines plotted on a bit-mapped display. circles in the figures represent pixels. due to the characteristics of a bit-mapped display, a straight line is drawn with the pixels arranged in a path differing slightly from an actual straight line. the same line is drawn in figures c.1 (a) and (b), but the algorithms are different, and so the pixel arrangements are also different. in both figures the line starts at the bottom left of the figure and is drawn dot by dot toward the top right corner. with the method shown in figure c.1 (a), the next dot drawn is to the right, or diagonally to the upper right, of the current dot. with the method shown in figure c.1 (b), on the other hand, the next dot drawn is to the right of, or directly above, the current dot. for the sake of convenience, the method in figure c.1 (a) is here called 8-point drawing, and that in figure c.1 (b), 4-point drawing. the difference between 8-point and 4-point drawing is illustrated in figure c.2. with 4-point drawing, the move to draw the next dot can be made in one of only four directions, up, down, left, or right (figure c.2 (b)). with 8-point drawing, moves can also be made in the four diagonal directions (figure c.2 (a)). (a) (b) figure c.1 two representations of a straight line on a raster display rev. 2.0, 09/02, page 317 of 366 (a) (b) figure c.2 comparison of (a) 8-point drawing and (b) 4-point drawing next, 8-point drawing straight line approximation is described, using figure c.3 (a). after pixel a is drawn, either pixel b or pixel c is selected; the basis for selection is proximity to an actual straight line. the same approach is also used in 4-point drawing (figure c.3 (b)). a comparison between 8-point drawing and 4-point drawing shows that closer approximation to a straight line can be achieved with 8-point drawing. however, the algorithm is correspondingly complex, requiring longer processing time. (a) a b c (b) actual straight line figure c.3 drawing dot determination process in (a) 8-point drawing and (b) 4-point drawing rev. 2.0, 09/02, page 318 of 366 readers interested in drawing algorithms can find further information in the sources listed below. 1. jerry van aken: curve-drawing algorithms for raster display, acm trams. graph. vol. 4, no. 2(april, 1985), 147C169. 2. j.e.bresenham: algorithm for computer control of a digital plotter, ibm syst. j. vol. 4, no. 1 (1965), 25C30 3. j.e.bresenham: a liner algorithm for incremental digital display of digital arcs, commum. acm. vol. 20, no. 2 (february 1977), 100C106 4. p.e.danielsson incremental curve generation, ieee trans. comput. vol. c-19 (september 1970), 783-793 5. w.j.jr.bernard: an improved algorithm for the generation of nonparametric curves, ieee trans. comput. vol. c-22, no. 12 (december 1973), 1052C1060 6. jerry van aken: an efficient ellipsedrawing algorithm, ieee comput. graph & appl. vol. 4, no. 9 (september 1984), 24C35 7. y.suenaga: a high-speed algorithm for the generation of straight lines and circular arcs, ieee trans. comput. vol. c-28, no. 10 (october 1979), 728C736 rev. 2.0, 09/02, page 319 of 366 appendix d package dimensions hitachi code jedec eiaj weight (reference value) fp-176 conforms 1.9 g unit: mm * dimension including the plating thickness base material dimension 26.0 0.2 24 0.10 133 176 45 88 132 89 144 0.10 m 0.5 26.0 0.2 1.70 max 1.40 *0.17 0.05 0 ? C 8 ? 1.0 0.5 0.1 0.10 0.05 * 0.22 0.05 1.25 0.20 0.04 0.15 0.04 figure d.1 package dimensions (fp-176) rev. 2.0, 09/02, page 320 of 366 appendix e display operating clock and screen synthesis the display operating clock (clk1) and possible fg screen, bg screen, and video screen display synthesis ranges are shown in tables e.1 to e.8. the following symbols are used in the tables: table e.1 32-bit ugm bus width, 66 mhz q2sd operating frequency display screen configuration screen synthesis possibility fg screen bg screen video screen 320 240 clk1: 6.5 mhz 480 240 9.5 mhz 640 240 14 mhz 640 480 25 mhz 800 480 33 mhz 8 bpp o o o o o 16 bpp o o o o o 8 bpp 8 bpp o o o o o 8 bpp 16 bpp o o o x x 16 bpp 8 bpp o o o x x 16 bpp 16 bpp o o o x x 8 bpp 16 bpp o o o x x 16 bpp 16 bpp o o o x x 8 bpp 8 bpp 16 bpp o o o x x 8 bpp 16 bpp 16 bpp o o o x x 16 bpp 8 bpp 16 bpp o o o x x 16 bpp 16 bpp 16 bpp o o o x x legend o: display synthesis possible x: display synthesis may not be possible \: display synthesis not possible bpp: bits per pixel note: 1. o if there is no video input rev. 2.0, 09/02, page 321 of 366 table e.2 32-bit ugm bus width, 60 mhz q2sd operating frequency display screen configuration screen synthesis possibility fg screen bg screen video screen 320 240 clk1: 6.5 mhz 480 240 9.5 mhz 640 480 25 mhz 800 480 33 mhz * 8 bpp o o o 16 bpp o o o 8 bpp 8 bpp o o o 8 bpp 16 bpp o o x 16 bpp 8 bpp o o x 16 bpp 16 bpp o o x 8 bpp 16 bpp o o x 16 bpp 16 bpp o o x 8 bpp 8 bpp 16 bpp o o x 8 bpp 16 bpp 16 bpp o o x 16 bpp 8 bpp 16 bpp o o x 16 bpp 16 bpp 16 bpp o x x note: * not possible since q2sd operating frequency > twice dot clock. video input is possible if the q2sd operating frequency is 64 mhz or higher. rev. 2.0, 09/02, page 322 of 366 table e.3 32-bit ugm bus width, 50 mhz q2sd operating frequency display screen configuration screen synthesis possibility fg screen bg screen video screen 320 240 clk1: 6.5 mhz 480 240 9.5 mhz 640 480 25 mhz 800 480 33 mhz * 8 bpp o o o 16 bpp o o o 8 bpp 8 bpp o o x 8 bpp 16 bpp o o x 16 bpp 8 bpp o o x 16 bpp 16 bpp o o x 8 bpp 16 bpp o o x 16 bpp 16 bpp o o x 8 bpp 8 bpp 16 bpp o o x 8 bpp 16 bpp 16 bpp o x x 16 bpp 8 bpp 16 bpp o x x 16 bpp 16 bpp 16 bpp o x x note: * not possible since q2sd operating frequency > twice dot clock. video input is possible if the q2sd operating frequency is 64 mhz or higher. rev. 2.0, 09/02, page 323 of 366 table e.4 32-bit ugm bus width, 40 mhz q2sd operating frequency display screen configuration screen synthesis possibility fg screen bg screen video screen 320 240 clk1: 6.5 mhz 480 240 9.5 mhz 640 480 25 mhz * 800 480 33 mhz * 8 bpp o o 16 bpp o o 8 bpp 8 bpp o o 8 bpp 16 bpp o o 16 bpp 8 bpp o o 16 bpp 16 bpp o o 8 bpp 16 bpp o o 16 bpp 16 bpp o o 8 bpp 8 bpp 16 bpp o x 8 bpp 16 bpp 16 bpp o x 16 bpp 8 bpp 16 bpp o x 16 bpp 16 bpp 16 bpp x x note: * not possible since q2sd operating frequency > twice dot clock. video input is possible if the q2sd operating frequency is 64 mhz or higher. table e.5 16-bit ugm bus width, 66 mhz q2sd operating frequency display screen configuration screen synthesis possibility fg screen bg screen video screen 320 240 clk1: 6.5 mhz 480 240 9.5 mhz 640 480 25 mhz 800 480 33 mhz 8 bpp o o o o 16 bpp o o o x 8 bpp 8 bpp o o o x 8 bpp 16 bpp o o x x 16 bpp 8 bpp o o x x 16 bpp 16 bpp o o x x rev. 2.0, 09/02, page 324 of 366 table e.6 16-bit ugm bus width, 60 mhz q2sd operating frequency display screen configuration screen synthesis possibility fg screen bg screen video screen 320 240 clk1: 6.5 mhz 480 240 9.5 mhz 640 480 25 mhz 800 480 33 mhz * 8 bpp o o o 16 bpp o o x 8 bpp 8 bpp o o x 8 bpp 16 bpp o o x 16 bpp 8 bpp o o x 16 bpp 16 bpp o o x note: * not possible since q2sd operating frequency > twice dot clock. table e.7 16-bit ugm bus width, 50 mhz q2sd operating frequency display screen configuration screen synthesis possibility fg screen bg screen video screen 320 240 clk1: 6.5 mhz 480 240 9.5 mhz 640 480 25 mhz 800 480 33 mhz 8 bpp o o o 16 bpp o o x 8 bpp 8 bpp o o x 8 bpp 16 bpp o o x 16 bpp 8 bpp o o x 16 bpp 16 bpp o o x table e.8 16-bit ugm bus width, 40 mhz q2sd operating frequency display screen configuration screen synthesis possibility fg screen bg screen video screen 320 240 clk1: 6.5 mhz 480 240 9.5 mhz 640 480 25 mhz * 800 480 33 mhz * 8 bpp o o 16 bpp o o 8 bpp 8 bpp o o 8 bpp 16 bpp o o 16 bpp 8 bpp o o 16 bpp 16 bpp o x note: * not possible since q2sd operating frequency > twice dot clock. rev. 2.0, 09/02, page 325 of 366 appendix f example of system configuration for superh hd64413a, a chip set of superh, is designed to facilitate the connection of the superh series cpu. for memory, sdram is directly connected. the hd64413a initializes sdram mode registers. for a dot clock signal clk1 for display and the operating clock (mclk) of hd64413a, a non- synchronous clock can be used. the display size is determined by the maximum clock frequency that can be input to clk1. for example, the display size when hd64413a operates under non-interlace mode is roughly 320 240 to 480 240 dots, and under interlace sink & video mode, it is about 640 480 dots. a synthetic display with external video signals can be performed by setting hd64413a to tv- synchronous mode and by supplying hsync, vsync, oddf and ckl1 from an external device to hd64413a. also, a video display can be performed by video-capturing by digitally encoding video signals. figure f.1 shows an example of the system configuration for the hd64413a. the hd64413a is an application specific ic which is oriented to the realization of a low-cost system for combined display of video, graphics, still picture, and cursor. rev. 2.0, 09/02, page 326 of 366 sync address data rendering clock display clock ugm address(14) data(32) ntsc hsync vsync video vcr sdram: 16m to 64m cde video stream encoder vin vqclk 320 240 frame buffer 0 frame buffer 1 binary work binary/multi- valued source select hd64413a q2sd r,g,b clk0 clk1 superh (cpu) video encoder analog in display list figure f.1 example of system configuration overview f.1 determination of clock the clocks supplied to hd64413a are clocks input to the clk1 pin and those input to the clk0 pin. the clocks input to the clk1 pin are used as clocks for display control, and the clocks input to the clk0 pin are used as operating clocks. 1. for the clk0 pin, the following clock type a or b can be used. a. method for using clocks output from ckio pin of superh when a superh (sh-3, sh-4) operating with 3.3v is used as the cpu, clocks output from the ckio pin can be used as input clocks for the clk0 pin. also, to increase the fan-out of ckio pin, input the output clock of the ckio pin to the clk0 pin of hd64413a via a buffer circuit. b. method for using clocks other than those output from ckio pin of cpu rev. 2.0, 09/02, page 327 of 366 clocks of 3.3v level can be used as input clocks for the clk0 pin. 2. input clocks for the clk1 pin must satisfy the following conditions: mclk [hz] 3 2 clk1 [hz] (clk1 33.3 mhz) mclk = n clk0 (n: either of multiple of 1, 2 or 4) f.2 setting of software weight the software weight cycle of superh is determined by the relationship of the external bus operating frequency (ckio) of superh and the internal operating frequency (mclk) of hd64413a. set the software cycle so that superh can detect the :$,7 signal output by hd64413a, taking into consideration the ac timing of both superh and hd64413a. here a case in which ckio = 20mhz and mclk = 66mhz are used using sh-3 is described. as shown in figure f.2, by setting the software cycle (tw) of superh to 2, the rule of twts and twth, which governs the :$,7 pin of superh can be observed and the hardware cycle (twx) between superh and hd64413a can be defined. (twas1 = 3 tcyc0 + 15 ns (max)) t1 tw tw ckio twx twts twth twas1 figure f.2 example of interface timing rev. 2.0, 09/02, page 328 of 366 f.3 special notes on connection when connecting superh to hd64413a, note the following: 1. when the initial value of &6 pin of superh is an input port and signals connected to the &6 and &6 pins of hd64413a are generated from this pin, pull up the &6 pin of superh so that the voltage level not to become unstable after canceling hardware reset. 2. when the dmac bu ilt in superh is used and the dack pin is set to active high by initial value setting, connect the inverted signal of dack pin to the dack pin of hd64413a by the external circuit. incidentally, use the dack pin set to active high, as is. 3. when using sh-4 for superh, invert signals output from the :$,7 pin of hd64413a by the external circuit and input them to the 5'< pin of sh-4. f.4 initialization procedures of address-mapped register standard procedures of setting initial value to the address-mapped register of hd64413a is described below. follow the steps 1 to 4. 1. set sres = 0, dres = 1 and den = 0 to the system control register and stop the display synchronous operation. additionally, do not allow access to ugm by superh and dmac after s etting these values and before the display synchronous operations start. 2. set initial values to registers between register addresses h 004 to h 04a and 056. in particular, depending on the initial values of each bit of h 056, initial values are required to be set to the registers related to these bits. 3. when displaying 8-bit/pixel displays or performing cursor display by combining gbm2 to gbm0, set initial values to the color palette register. 4. set sres = 0 and dres = 0 to the system control register and start display synchronous operations. by setting this way, superh can make access to ugm. add itionally, to enable the graphics drawn by hd64413a to be checked, normally the dbm of system control register is specified with auto rendering mode or manual display change mode. rev. 2.0, 09/02, page 329 of 366 f.5 memory assignment f.5.1 memory mapping of hd64413a the address-mapped registers of hd64413a and ugm are mapped in the cache through space of memory space of superh. an example of memory map using a 64-mbit synchronous ram as ugm is shown in figure f.3. also, pins a22 to a1 of hd64413a require the ugm address of hd64413a to be input directly. in this example, a1 to a22 are used as address signals for directly showing the ugm address. for example, when access is made by superh to address h 000000 of ugm, clear all a22 to a1 pins of hd64413a to 0. in figure f.3, ugm is p laced from h a8000000 so that access is made to the cache through space when superh makes access to ugm. h'a8000000 h'a87fffff h'a8800000 h'a88002ff h'a8ffffff ugm 32 mbytes cache through space pins md3 = 1, md4 = 0 cs1 space, normal space, cache through area 16-bit space image space of address-mapped register address-mapped register figure f.3 example of memory mapping (using sh7709) rev. 2.0, 09/02, page 330 of 366 f.5.2 example of area placement in ugm an example of area placement in ugm is shown in figure f.4. this figure shows only an example meaning that other area placement styles are allowed. 1. frame buffer area (fb0, fb1) under double-buffer control, these areas are used as a display area (screen coordinates) and drawing area (rendering coordinates). for the display addresses (dsa0, dsa1) of these areas, set the ugm addresses that correspond to every 256-dot position touching y-axis. 2. video store area (v0, v1, v2) when using the video capture function, the captured data streams are stored in these areas. the areas are used in order of v0, v1 and v2 each time a synchronous signal is input to the 996 pin. here the read size is 320 240 pixels. for the display addresses of these areas (vsar0 to vsar2), set the ugm addresses corresponding to every 16-dot position along y-axis and every 32-dot position along x-axis, considering that ugm is 16 b it/pixel. additionally, when the video capture function and video window are not displayed, these areas are not used and are not necessary. 3. work area (bwarea) this area is used as a work area. the maximum pixel of x-axis of work coordinates is the pixel quantity specified by the mwx bit of rendering mode register. accordingly, regardless of the gbm bit of rendering mode register, the memory capacity required as work coordinates is (pixel quantity specified by mwx bit) (display pixel quantity along y- axis)/8[bytes]. for work area addresses (wash, wasl), set ugm addresses corresponding to every 16-dot position touching y-axis. additionally, when the drawing of optional patterns, such as polygons, is not performed, this area is not used and is not necessary. 4. display list area (dl0, dl1) these areas are used for storing display lists. either one of dlo and dl1 is used as the read area for hd64413a to fetch display lists, and the other as the write area for superh to place display lists. dl0 and dl1 are used alternately by software control. display list start addresses (dlsah, dlsal) can be sp ecified with optional word (16-bit) addresses. 5. cursor 1, 2 area (cu1, cu2) these areas are used for storing the shape patterns of cursors. for hd64413a, two cursors can be displayed, so each shape is stored respectively in cu1 and cu2. also, as cursors themselves are displayed as 8-bit/pixel, surely set the display colors of cursors in the color palette. rev. 2.0, 09/02, page 331 of 366 additionally, for both cu1 and cu2, the memory capacity used is 2kb. 6. display size 640 240 dots (the maximum of 640 480 dots) 7. background area (bg) this area is used for a background screen. the start address for this area is specified in screen coordinates. 0 16 dots 480 496 512 cu1 cu2 v0 v1 v2 dl0 dl1 640 1023 dots 0 fb0 fb1 992 1231 h'000000 h'0f0000 h'0f8000 h'100000 h'1f0000 480 kbytes 12 kbytes bwarea 12 kbytes 12 kbytes 32 kbytes 32 kbytes h'00d000 960 256 768 h'015000 h'07d000 h'105000 h'17d000 16 dots 16 dots dl0, dl1: area for command double-buffer control fb0, fb1: area for fg plane bwarea: area for work coordinates cu1: area for cursor 1 cu2: area for cursor 2 v0 to v2: area for video buffer bg figure f.4 ugm memory map rev. 2.0, 09/02, page 332 of 366 f.5.3 address seriation in ugm as shown in figure f.5, when ugm is viewed from superh, ugm addresses look as a series of tiles arranged by memory unit. thus, by using more than one memory units that were not used in area assignment of fb0, fb1, etc., the space can be used as a memory space with a series of addresses. in case of hd64413a, items that can be placed in a memory space with a series of addresses include binary and multi-valued sources and cursor patterns, so normally these are placed in this area. for example, on the right of fb0, a memory space with a series of addresses having (1024-640) pixels 16 lines = 6114 pixels from the position x = 640, y = 0, or a capacity of 12 kbytes from the relationship 1 pixel = two bytes, can be secured. here cu1 assignment or others is performed. 16 lines ugm 0th line 16th line 32nd line 32 or 16 pixels 32 or 16 pixels memory unit when ugm is viewed from superh, ugm addresses turn down within a range of 32 16 pixels (8-bit/pixel) or 16 16 pixels (16-bit/pixel) and go to the top left of the following memory unit. figure f.5 ugm address transition overview rev. 2.0, 09/02, page 333 of 366 f.6 special notes on data transfer to ugm to transfer data such as binary data and display lists by superh or the dma contro ller to ugm, first do the initial setting to the address-mapped register of hd64413a and start display synchronous operations so as to enable data transfer between superh and ugm. since an access made by superh or the dma contro ller to ugm may stop d ata transfer when display synchronous operations are not performed, do not attempt to make access to ugm when display synchronous operations are not performed. additionally, there is only one bus master that can make access to ugm. accordingly, when the dma mode in sys tem control register of hd64413a is normal mode, only superh can make access to ugm. likewise, when the dma mode is dma transfer mode, only the dma controller can make access to ugm. data transfer is possible even in the midst of drawing processing by hd64413a. when the dmac bu ilt in superh is used, surely check te (transfer end flag bit) and then the dmf flag of s tatus register of hd64413a before finishing dma transfer. rev. 2.0, 09/02, page 334 of 366 appendix g example of display control g.1 determination of display size display pixels along horizontal direction (hdot) are required to be values satisfying the following formula. for example, if clk0 = 33mhz, n = 1, hd = 44.7 m /s, hdot must be 737 pixels or less. also, the frequency of display dot clock (clk1) must be clk1 = hdot/hd (hz). hd ht hdot display area ht > hd hdot hd clk0 n 2 = mclk where, n is a multiple of q2sd clk0 is a clock (hz) input to the clk0 pin of q2sd. ht: cycle (sec) hd: display time in (sec) hdot: quantity of display pixels along horizontal direction (pixel) figure g.1 example of display timing rev. 2.0, 09/02, page 335 of 366 g.2 selection of display screen hd64413a has the following three display screens: 1. foreground screen displayed at the frontmost. it can be displayed with 8 or 16 bit/pixel and is used mainly for realizing dynamic images in drawing processing. 2. background screen displayed at the rearmost. it can be displayed with 8 or 16 bit/pixel and is used mainly for realizing scroll by pixel. 3. video screen displayed between the foreground and background screens. it is used for displaying the stream data captured by the video capture function. each display screen can be selected as the foreground screen by the fbd bit, the background screen by the bg bit, and the video window by the vwe bit. rev. 2.0, 09/02, page 336 of 366 g.3 setting of synchronous signal to enable display control, hd64413a requires synchronous signals to be set in the address- mapped register. an example of register setting of the synchronous signals used for this application note is shown below: 1. setting example of synchronous signals when the tv synchronous mode is master mode and the scan mode is non-interlace is shown. the display size is 320 240 dots. here, clk1 = (horizontal display pixel)/(xw time) (hz). xs (9.08 m s) xw (44.7 m s) hsw (4.47 m s) hc (63.56 m s) vc=262 rasters yw=240 rasters effective display range vsw=3 rasters ys=16 rasters figure g.2 example of display timing under non-int erlace mode rev. 2.0, 09/02, page 337 of 366 table g.1 setting example of variables ((tvm1,0) = (0,0), (scm1,0) = (0,0)) variable calculation formula value in display example hsw 4.47 m s clk1 32 xs 9.08 m s clk1 65 xw 44.7 m s clk1 320 hc 63.56 m s clk1 455 clk1 = 7.159 mhz table g.2 register setting example ((tvm1,0) = (0,0), (scm1,0) = (0,0)) register calculation formula (master mode) setting value in display example dsx xw 320 dsy yw 240 hds hsw + xs - 11 68 hde hsw + xs - 11 + xw 406 vds ys - 214 vde ys - 2 + yw 254 hsw hsw - 131 hc hc - 1 454 vsp vc - vsw - 1 258 vc vc - 1 261 rev. 2.0, 09/02, page 338 of 366 2. setting example of synchronous signals when the tv synchronous mode is master mode and the scan mode is interlace & video mode is shown. the display size is 640 480 dots. here, clk1 = (horizontal display pixel)/(xw time) (hz). xs (9.08 m s) xw (44.7 m s) hsw (4.47 m s) hc (63.56 m s) vsw=3 rasters vc=262 rasters yw=240 rasters effective display range (odd-number field) vsw=3 rasters vc=262 rasters yw=240 rasters effective display range (even-number field) 525 rasters ys=16 rasters ys=16 rasters figure g.3 example of display timing under int erlace sink & video mode rev. 2.0, 09/02, page 339 of 366 table g.3 setting example of variables ((tvm1,0) = (0,0), (scm1,0) = (1,1)) variable calculation formula value in display example hsw 4.47 m s clk1 64 xs * 9.08 m s clk1 131 xw 44.7 m s clk1 640 hc 63.56 m s clk1 910 clk1 = 14.318 mhz note: when using a video encoder, determine xs so that the effective display range does not overlap the color burst. table g.4 register setting example ((tvm1,0) = (0,0), (scm1,0) = (1,1)) register calculation formula (master mode) setting value in display example dsx xw 640 dsy yw 2 cycles of 96<1& 240 hds hsw + xs - 11 184 hde hsw + xs - 11 + xw 824 vds ys - 214 vde ys - 2 + yw 254 hsw hsw - 163 hc hc - 1 909 vsp vc - vsw - 1 258 vc vc - 1 261 rev. 2.0, 09/02, page 340 of 366 g.4 setting and changing register values related to display control g.4.1 setting of color palette the color palette of hd64413a is designed to write or read color palettes by two-word continuous access. so, when setting values to color palettes, surely set registers containing g and b, following a register containing r. likewise, when reading values from color palettes, surely read out registers containing g and b, following a register containing r. g.4.2 switching procedure of synchronous mode a change in synchronous mode, from master mode to tv synchronous mode and the like, is performed by way of synchronous switching mode. switching to synchronous switching mode can be performed by setting tvm1 = 0, tvm0 = 1. also, since hd64413a does not refresh ugm under synchronous sw itching mode, set dres = 1, den = 0 and switch the mode to one under which hd64413a refreshes ugm, before entering synchronous switching mode. procedures are shown below. additionally, as hd64413a refreshes ugm wh ile dres = 1, den = 0 is valid, do not attempt access to ugm by superh or dmac. switching procedure to synchronous switching mode: 1. set bg = 0, vwe = 0, ce1 = 0, ce2 = 0. 2. set dres = 1, den = 0. now only refreshing to ugm can be performed. 3. set tvm1 = 0, tvm0 = 1. hd64413a switches to synchronous switching mode. returning procedure from synchronous switching mode: 4. input a clock to the clk1 pin. for a switch to tv synchronous mode (tvm1 = 1, tvm0 = 0), also input signals to (;+6<1& , (;96<19 and 2'') pins. 5. to change the display size, setting values to the address-mapped register of hd64413a. 6. by setting tvm1 = 0 and tvm0 = 0, or tvm = 1 and tvm0 = 0, the input clock from the clk1 pin is effective. further, set bg = 1, vwe = 1, ce1 = 1, ce2 = 1, as needed. 7. set dres = 0, den = 1. after internal updating, hd64413a starts displaying. g.5 use of cursor display the hd64413a can display two cursors with 32 32 pixels placed in the ugm. one cursor has two shape data: cursor blink shape a and cursor blink shape b. they are alternatively displayed rev. 2.0, 09/02, page 341 of 366 at the timing specified by bli nka and blinkb. therefore, an area of continuous 2-kbyte addresses per one cursor is required. using four memory units in the horizontal direction can allocate the continuous 2-kbyte area in the ugm as shown in figure g.4. for d etails of a single memory unit, see section f.5.3, address seriation in ugm. ugm cursor area start address four memory units cursor blink shape a cursor blink shape b figure g.4 cursor allocation when the hd64413a displays a cursor, a cursor shape data is first read from an address specified by the cursor area start address register. the cursor is painted by referencing the cursor shape data and is displayed. rev. 2.0, 09/02, page 342 of 366 appendix h example of drawing control h.1 example of starting drawing hd64413a performs drawing on rendering coordinates and work coordinates based on command groups called display lists. the drawing procedures are shown below: 1. using superh, place lc ofs and sclip co mmands as a display list to ugm. this display list is intended to set initial values of the local offset and system clip ranges of hd64413a. 2. to synchronize the frame change timing and draw start timing, place the vbkem command following the display list placed in 1 to ugm using superh or use the fr ame change function specified by the dbm bit in the system control register ( sysr). 3. following the display list placed in 2, place the display list using pol ygon4-series commands and the like to ugm using superh to let hd64413a perform drawing. 4. following the display list placed in 3, place the trap command to show the end of display listing. at this moment, the display list preparation is finished. 5. after setting the rendering start address, set 1 to rs bit. by this register setting, you can let hd64413a perform drawing. h.2 example of frame change by internal updating an example of a frame change by internal updating is described below. in this case, a frame change is performed by internal updating, while fixing the dbm bit at manual display change mode and controlling display start addresses dsa0, dsa1, and rsar by superh. when using the suspend/resume function of drawing, method by which the draw start address and display start address can be controlled is effective. in this case, first the dbf bit in status register should be checked to judge which of dsa0 or dsa1 is the register that d etermines the display start address. when dbf = 0, dsa0 is the register d etermining the display start address. likewise, when dbf = 1, dsa1 is the register d etermining the display start address. table h.1 shows the relationship of dbf, dsa0 and dsa1. table h.1 relationship of dbf and display s creen (fg) dsa0 dsa1 dbf = 0 display screen drawing screen dbf = 1 drawing screen display screen as an example, control procedures 1 to 4 of dsa0 and dsa1 of a case dbf = 0 are shown below: rev. 2.0, 09/02, page 343 of 366 1. wait until the internal updating cycle is finished. to confirm the end of internal updating, clear frm bit and see that the frm bit becomes 1. 2. using the wpr command, set in dsa0 the display start address of a pos ition to do displaying in the next internal updating. the display start address set to dsa0 is not ref lected as an effective value. this setting value becomes effective only passing an internal updating. 3. using the wpr command, set 1 to rsae and the draw start address to rsar. 4. after transferring display lists, read dummy data from the ugm and then set the rs bit in the system control register to 1 to start drawing. by repeating the steps 1 to 4 above, the display start address set to dsa0 becomes eff ective by internal updating and frame changing is enabled. the drawing and display timing using the frame change by internal updating are shown in figure h.1: rev. 2.0, 09/02, page 344 of 366 referencing dsa0 by internal updating. (display fb1) display screen display fb1 display fb0 display fb1 dsa0 ( display control) rsar ( drawing control) processing by q2sd (1) (2) (3) (4) using frm bit, wait until internal updating is finished using wpr, set the next display start address (fb0) using wpr, set the next draw start address (fb0) drawing referencing dsa0 by internal updating (display fb0) referencing dsa0 by internal updating (display fb1) using frm bit, wait until internal updating is finished using frm bit, wait until internal updating is finished using wpr, set the next display start address (fb1) using wpr, set the next display start address (fb0) using wpr, set the next draw start address (fb0) using wpr, set the next draw start address (fb1) using wpr, set the next draw start address (fb1) drawing drawing drawing figure h.1 display/drawing control timing chart (dbf = 0) rev. 2.0, 09/02, page 345 of 366 h.3 using example of draw commands h.3.1 drawing polygons drawing polygons on rendering coordinates using hd64413a can be performed by using work reference, one of rendering attributes, and work coordinates. drawing procedures by hd64413a are shown below: 1. to clear the work area, execute the clrw command. 2. using the ftrap command, draw on work coordinates the shape of polygon to draw. 3. using the polygon4c co mmand of which the work bit with rendering attribute is set to 1, draw a polygon with the shape drawn on the work coordinates. 4. using the line command, draw an outline of the polygon. practically, the display list to perform the above procedures is generated by superh, and drawing is performed by hd64413a based on the display list generated. h.3.2 drawing optional shapes an optional shape which is a fixed shape with binary pattern having been placed on work coordinates by partially referencing can be drawn. before placing a binary pattern on work coordinates, the work coordinates must be zero-cleared. to avoid concurrent drawing on work coordinates by superh and hd64413a, the zero-clearing of the work coordinates is performed not by the clrw command but directly by superh. h.3.3 drawing circles and ellipses to draw a circle or an ellipse by hd64413a, the orbit of ellipse is calculated by superh, and drawing is performed by the line command using the calculated result as parameters. using bresenhams circle algorithm, the ellipse orbit is worked out. drawing a circle is enabled by converting the x, y radiuses of ellipse to same dot quantities. when drawing is required to be performed in a work area, the line command should be used. h.3.4 drawing using source data when using a draw command that references a source by hd64413a, generally it is necessary to judge whether or not source data is stored in ugm on the app lication software side. in a certain system, the judgment is difficult or processing requires time. as an example to avoid this, there is one method that relates the draw command and the reference position of source by including source data in the display list. rev. 2.0, 09/02, page 346 of 366 to embed source data into the display list, place the jump co mmand immediately after the draw command so that the source data is skipped as shown in figure h.2. when a multi-valued source is included in the display list, the same method can be applied. in this case, use the polygon4a co mmand by setting 1 to the lni bit with rendering attribute. jump polygon4b binary source data next command display list relative referencing relative branching figure h.2 example of referencing and branching h.3.5 expressing 3d space a solid graphics formed with multiple rectangles are rotated by rotating each rectangle. processing procedures are described below: 1. define the rectangles that are expressed with 3d coordinates. a set of the rectangles defined with the function forms one solid graphic. 2. do rotational operation of coordinate values for each rectangle. 3. determine the order of drawing rectangles. drawing order is from the depth to the front. first the mean value of z values of each rectangle is calculated, and the order is set based on the results. in a bubble sorting which is easily described by a source program, sorting is performed by approximately n n times where the quantity of elements to be sorted is n. in a high-speed sorting method like heap sorting is used, sorting can be finished by approximately n log n times. 4. convert 3d coordinate values into 2d coordinate values for each rectangle. firstly, a position in which the z value of each vertex exists in the depth of z-axis is given by the ratio of the position to the z value. then, conversion is achieved by multiplying each of four vertices by its ratio. 5. using the order determined in 3 and the 2d coordinate values obtained in 4, drawing is performed on ugm with the polygon4c co mmand as a display list. rev. 2.0, 09/02, page 347 of 366 after finishing the above procedures, the display list is generated on ugm, and a 3d sp ace can be expressed by drawing using hd64413a. h.4 special notes on using draw commands h.4.1 notes on the relationship of local offset and cu rrent pointer local offset and the current pointer are given their respective values by the order of command execution. so, place commands while taking into consideration the relationship of local offset and the current pointer. the priority order of command placement is shown below. draw commands having low priority are to be placed first. 1. lcofs command sets the initial value of local offset. 2. rlcofs command moves local offset by a relative value to the current local offset. 3. move command sets the current pointer by adding the current local offset. 4. remove command moves the current pointer by a relative value to the current pointer currently used. h.4.2 notes on using relative-series commands commands that control coordinate parameters on relative coordinates are called relative-series commands. when using the relative-series commands, it is necessary to generate a current pointer using the move command and the like beforehand. also, commands other than relative- series commands use the current pointer as a register for operation and break it. therefore, when using relative-series commands performing drawing, do not insert other commands between relative-series commands. rev. 2.0, 09/02, page 348 of 366 h.4.3 notes on using source data when hd64413a uses the binary and multi-valued sources placed in ugm, source d ata is taken to the source buffer existing in hd64413a, and drawing is performed using the accumulated source data. the source buffer has a capacity of 16 words, and hd64413a stores every 32-byte data to the source buffer each time the ugm address passes a 16-word border. b ecause of this, when using binary and mullet-valued sources, it is necessary to let hd64413a perform drawing while taking into consideration to cause source buffer updating. also, how the source buffer updating is performed is determined by the styl bit with rendering attribute as described in 1 and 2 below: 1. when styl with rendering attribute is set to 0 when styl = 0, consideration must be taken so as to cause source buffer updating when the source capacity is within 32 bytes. the following methods can be considered: a. specify different source addresses for each command. for example, when referencing binary sources within 32 bytes by the polygon4b command, this method can be performed by specifying different addresses for each of polygon4b co mmand parameters source addressh and source addressl. b. use transparent designation by this method, by preparing binary sources exceeding 32 bytes, only the binary source of a necessary part is drawn when drawing using the draw command of which transparent designation is enabled. 2. when styl with rendering attribute is set to 1 when styl = 1, source referencing is performed repeatedly. accordingly, when a source referencing is finished at an address within 32 bytes, counting from the source reference start address, consideration must be given so as to cause source buffer updating. the following methods can be considered: a. specify different source addresses for each command. for example, when referencing binary sources within 32 bytes by the polygon4b command, this can be performed by specifying different addresses for each of polygon4b co mmand parameters source addressh and source addressl. rev. 2.0, 09/02, page 349 of 366 h.5 functions to support drawing processing h.5.1 suspension/resumption of drawing suspension/resumption of drawing is intended to support drawing functions and is supported from hd64412 (q2i) on. this function is used when doing drawing processing to the frame buffer (fb) during a background screen (bg) drawing or for forcible interruption with drawing processing. use of suspension/resumption of drawing is described below. additionally, the function is available only when 10 is set to the dbm bit of system control register and the double-buffer control is fixed at manual display change. suspension of drawing: suspension of drawing is intended to suspend the drawing that is currently being performed. suspension of drawing can be performed by setting 1 to the rbrk bit of system control register ( sysr). setting 1 to the rbrk bit by superh, hd64413a sets values set to the register inside lsi (current pointer, local offset, clipping range, return address of gosub co mmand) to rendering control register 2 at the top of next command that follows after the execution of current draw command is finished, and suspends the drawing. to determine suspension of drawing by superh, after setting 1 to the rbrk bit, read out the tra and brk bits. if the tra bit is 1, meaning that drawing is finished by executing the trap command, and not suspension by rbrk, do not resume drawing thereafter. if the brk bit is 1, it means suspension of drawing. thus, suspension of drawing can be judged by confirming brk = 1. when the brk bit becomes 1, read values set to the rendering control register 2, draw start address enable (rsae) of rendering mode register, draw start address register (rsar) and the command status register (cstr) by superh software processing, and shelter them on the superh memory. sheltered values are used when resuming the suspended drawing. thereafter, generate the display list to draw during suspension and execute. resumption of drawing: resumption of drawing is intended to resume a drawing suspended by suspension of drawing. to resume the drawing, place a display list for resuming drawing to ugm using superh, start resumption of drawing to the display list (by s etting 1 to the rs bit of system control register) and confirm that the rs bit returns to 0. the composition of display list for resuming drawing is described in 1 to 8 below: order of display list commands used to resume drawing (1 to 8 in this order) 1. wpr command: sets the draw start address register values sheltered when suspending drawing to the draw start address register (rsar). 2. wpr command: sets the draw start address enable values sheltered when suspending drawing to the start address enable (rsae). rev. 2.0, 09/02, page 350 of 366 3. wpr command: sets the return address of gosub co mmand sheltered when suspending drawing to the return address register (rtnr). 4. uclip command: returns the uclip values sheltered when suspending drawing. 5. sclip command: returns the sclip values sheltered when suspending drawing. 6. lcofs co mmand: returns the local offset values sheltered when suspending drawing. 7. move co mmand: returns the current pointer values sheltered when suspending drawing. 8. jump co mmand: returns the command status register values sheltered when suspending drawing. rev. 2.0, 09/02, page 351 of 366 appendix i drawing performance figures i.1 to i.3 show graphs of hd64413a drawing performance. the graphs show the time required for drawing within the range 320 (h) 240 (v). 2.4 (ms) 2.23 2.2 2.19 2.0 1.8 1.81 1.6 1.52 1.4 1.43 1.38 1.32 1.29 1.2 0.0 1.62 320 (h) 240 (v) 640 (h) 2480 (v) 800 (h) 2480 (v) 8-bit/pixel drawing 16-bit/pixel drawing display size drawing time conditions ? 320 (h) 240 (v); clk1 = 7.15 mhz ? 640 (h) 480 (v); clk1 = 25 mhz ? 800 (h) 480 (v); clk1 = 33 mhz ? mclk = 66 mhz ? video capture not performed ? 32-bit ugm bus width ? fg only displayed fg screen display fg screen display fg screen + bg screen display figure i.1 polygon4c drawing performance when fst = 0 (drawing range: 320 (h) 240 (v)) rev. 2.0, 09/02, page 352 of 366 1.8 (ms) 1.68 1.6 1.4 1.2 1.0 0.91 0.75 0.84 0.78 0.70 0.68 0.6 0.0 320 (h) 240 (v) 640 (h) 480 (v) 800 (h) 480 (v) 8-bit/pixel drawing 16-bit/pixel drawing display size drawing time conditions ? 320 (h) 240 (v); clk1 = 7.15 mhz ? 640 (h) 480 (v); clk1 = 25 mhz ? 800 (h) 480 (v); clk1 = 33 mhz ? mclk = 66 mhz ? video capture not performed ? 32-bit ugm bus width fg screen display fg screen + bg screen display fg screen display figure i.2 polygon4c drawing performance when fst = 1 (drawing range: 320 (h) 240 (v)) rev. 2.0, 09/02, page 353 of 366 2.4 2.6 (ms) 2.41 2.2 2.0 1.8 1.96 1.6 1.48 1.4 1.38 1.2 0.0 320 (h) 240 (v) 640 (h) 480 (v) 8-bit/pixel drawing 16-bit/pixel drawing display size drawing time conditions ? 320 (h) 240 (v); clk1 = 7.15 mhz ? 640 (h) 480 (v); clk1 = 25 mhz ? 800 (h) 480 (v); clk1 = 33 mhz ? mclk = 66 mhz ? video window size: 320 (h) 240 (v) ? video capture size: 320 (h) 240 (v) ? 32-bit ugm bus width fg screen display + video window display + video capture fg screen display + video window display + video capture fg screen + bg screen display + video window display + video capture figure i.3 polygon4c drawing performance when fst = 0 (drawing range: 320 (h) 240 (v)) rev. 2.0, 09/02, page 354 of 366 appendix j usage of video capture function j.1 example of video capture settings j.1.1 example of interlace composite capture description video data with 640 480 is captured in interlace mode. video screen data with 640 480 is displayed on the full-size screen. q2sd register setting video decoder initialization: interlace output 640 480 mode memr : h 0031 (64 mbits 32 bits 1) dsmr : h 0003 (non-interlace, master mode, refresh 3) remr : h 0040 (bg: off, fg/bg: 8 bits, 1024 mode) dsx : h 0280 (640) dsy : h 01e0 (480) dsa0r : h 0000 (b 0000000) dsa1r : h 0008 (b 0080000) dsmr2 : h 0409 (video display on, cursor1 display off, cursor2 display off, fg display off, yc ? rgb conversion on) hvpr : h 0000 (x coordinate 0) vvpr : h 0000 (y coordinate 0) vsah0 : h 0018 (b 0180000) vsal0 : h 0000 vsah1 : h 0028 (b 0280000) vsal1 : h 0000 vsah2 : h 0038 (b 0380000) vsal2 : h 0000 vsizex : h 0280 (640) vsizey : h 01e0 (480) vimr : h 0005 (yc ? rgb conversion off, inter lace composite capture, horizontal reduction ratio 1, vertical reduction ratio 1) rev. 2.0, 09/02, page 355 of 366 fg0 fg1 800000 100000 280000 380000 480000 7fffff 640 0 1023 480 480 480 480 480 640 480 video 1 display list memory map video 2 video 3 figure j.1 interlace composite capture j.1.2 example of modifying video data size description video data with 640 480 is captured. both the horizontal and vertical reduction ratios are specified to 1/4 and the video display positions are shifted by 80 in the x and y direction. the video screen data with 160 120 is displayed on the screen with 320 240. q2sd register setting bt initialization program: monitor command ww (video display size 640 480 mode) memr : h 0011 (16 mbits 16 bits 2) dsmr : h 0003 (non-interlace, master mode, refresh 3) remr : h 0400 (bg: on, fg/bg: 8 bits, 512 mode) dsx : h 0140 (320) rev. 2.0, 09/02, page 356 of 366 dsy : h 00f0 (240) dsa0r : h 0000 (b 0000000) dsa1r : h 0002 (b 0020000) dsmr2 : h 0409 (video display on, cursor 1 display off, cursor 2 display off, fg display off, yc ? rgb conversion on) hvpr : h 0050 (x coordinate 80) vvpr : h 0050 (y coordinate 80) vsah0 : h 0008 (b 0080000) vsal0 : h 0000 vsah1 : h 0008 (b 0100000) vsal1 : h 0000 vsah2 : h 0018 (b 0180000) vsal2 : h 0000 vsizex : h 00a0 (160) vsizey : h 0078 (120) vimr : h 0385 (yc ? rgb conversion off, inter lace composite capture, horizontal reduction ratio 1/4, vertical reduction ratio 1/4) rev. 2.0, 09/02, page 357 of 366 fg0 fg1 3f3ff 1f3ff 80000 100000 180000 37fffe 320 0 512 240 240 240 240 240 80 240 120 640 320 480 160 video 1 video 2 video 3 display list memory map video decoder output horizontal reducation ratio: 1/4 video decoder output display screen figure j.2 interlace composite capture (horizontal and vertical reduction ratios = 1/4) rev. 2.0, 09/02, page 358 of 366 j.2 example of usage of captured data j.2.1 when displaying captured data on realtime video screen when the vie bit in vimr is set to 1 and the vwe bit in dsmr2 is set to 1, the latest video stream data stored in the video storage area is displayed realtime. in this case, either of the following settings must be made. when the rgb bit in vmir is 1, clear the vwry in dsmr2 to 0. when the rgb bit in vmir is 0, set the vwry in dsmr2 to 1. j.2.2 when handling captured data as multi-valued source data when vie = 0 is set and video capturing is stopped, the video storage area where the latest video stream data is stored in the vid1,0 bits of vimr is shown. if video capture function is executed when the rgb bit in vmir is 1, it is possible to reference the video storage area specified by vid1,0 as a 16-bit/pixel multi-valued source. additionally, vid1,0 has no meaning while video capturing is going on (vie = 1). to reference vid1,0, first stop video capturing (vie = 0). description video captured data is converted into rgb format and stored in the bg screen. at this time, the video captured data as multi-valued source is mapped onto figures and is drawn using drawing function. q2sd register setting bt initialization program: monitor command ww (video display size 640 480 mode) memr : h 0010 (16 mbits 16 nits 2) dsmr : h 0405 (non-interlace, master mode, refresh 5, bg: on) remr : h 0001 (fg/bg: 16 bits, 512 mode) dsx : h 0140 (320) dsy : h 00f0 (240) dsa0r : h 0000 (b 0000000) dsa1r : h 0004 (b 0040000) bgsx : h 0000 (0) bgsy : h 0200 (512) dsmr2 : h 0001 (video display on, cursor 1 display off, cursor 2 display off, fg display on, yc ? rgb conversion off) hvpr : h 00a0 (x coordinate 160) vvpr : h 0078 (y coordinate 120) rev. 2.0, 09/02, page 359 of 366 vsah0 : h 0008 (b 0080000) vsal0 : h 0000 vsah1 : h 0008 (b 0081400) vsal1 : h 1400 vsah2 : h 0009 (b009c100) vsal2 : h c100 vsizex : h 00a0 (160) vsizey : h 0078 (120) vimr : h 0183 (yc ? rgb conversion on, non-interlace capture, horizontal reduction ratio 1/4, vertical reduction ratio 1/4) 320 bg fg0 fg1 40000 1f3ff 80000 100000 110000 37fffe 320 0 512 240 240 240 240 240 320 0 2 bg bg bg 1 video display list 0 display list 1 memory map display screen data captured on the fg is rotated and activated. figure j.3 example of video data usage rev. 2.0, 09/02, page 360 of 366 no ye s no ye s no ye s no ye s no ye s no ye s no ye s no ye s no ye s no ye s ye s no ye s no start clk0 exceeds 64 mhz? reconfigure system. clk0 must exceed 64 mhz. reconfigure system. modify size and configuration (8/16) for display screen. reconfigure system. memory must be x32 product. clk1 exceeds 64 mhz? bus width of ugm is 32 bits? display mode is non-interlace? display mode is interlace sync? display monitor is interlace type? interlace non-interlace screen size is correct? modify screen size blurring on screen? reconfigure system. modify display method. data correctly composed? invert odev in dsmr video capture mode is non-interlace? video capture mode is non-interlace (even- or odd-only)? blurring on displayed video screen? use external video decoder signals to perform external tv sync reconfigure system. modify display method. something wrong with displayed video screen? end a b figure j.4 q2sd video setting flow (1) rev. 2.0, 09/02, page 361 of 366 ye s no ye s no ye s no display monitor is interlace type? interlace screen size is correct? blurring on screen? video capture mode is non-interlace? reconfigure system. modify display method. modify screen size end a non-interlace figure j.5 q2sd video setting flow (2) rev. 2.0, 09/02, page 362 of 366 ye s ye s no no ye s ye s ye s no no b display monitor is interlace type? interlace non-interlace screen size is correct? modify screen size blurring on screen? video capture mode is non-interlace? video capture mode is interlace composite? reconfigure system. modify display method. something wrong with displayed video screen? reconfigure system. modify display method. end figure j.6 q2sd video setting flow (3) rev. 2.0, 09/02, page 363 of 366 j.3 video decoder j.3.1 field control by video decoder 66 mhz 16 8 8 cpu-bus 32 q2sd sdram 28.63 mhz pca9515 5v/3.3v sdram clk0 vhs vvs vodd vqclk vin7 vin0 scl sda hreset ntsc video decoder yin vreset field qclk vd15 to to to vd8 vd7 vd0 sda scl oe +5 v +3.3 v vin 10 m f 75 w i 2 c driver figure j.7 example of connection of video capture circuit since the video decoder in this figure is a mixed-analog-digital device with a 5-v power-supply and a 3.3-v digital interface, the i 2 c interface requires conversion from 5 v to 3.3v. the q2sd and video decoder are only connected by the eight data lines (vin0 to vin7), sync- signal lines (vhs and vvs), sync-clock line (vqclk), and f ield-signal line (vodd). the i 2 c driver connected to the video decoder via the pca9515 is used to set the video decoder by the cpu. the combination of fields in interlacing by the q2sd can be switched to match the source. since the combination of fields (top and bottom fields) is not explicitly stipulated in the ntsc specification, two combinations are possible. most video decoders, therefore, include a polarity- inversion function for the field signal. rev. 2.0, 09/02, page 364 of 366 frame1234 1234 top1357 2468 bottom24681357 format top first (tv, dvd) bottom first an example of the timing of the output of data in the interlaced operation of an ntsc video decoder is shown in figure j.8. for most video decoders, the timing of the transitions of the field signal in interlaced operation differs between the odd and even fields. vreset hreset clk 2 active qclk vd[15:8] fild (odd) fild (even) 1h 2h figure j.8 example of interlaced data output timing for decoder j.3.2 video decoder settings the q2sds video-input function should be configured to operate with a video decoder which outputs data in the 8-bit streaming video format prescribed in itu-601. the operation of the following decoders has been examined at our company: the bt815a, bt817a, bt819a, bt827a/b, bt829a/b, and bt835. all of these decoders are manufactured by rockwell. when the video decoder is connected to the q2sd, the video decoder is controlled via the i2c interface. the video decoder thus must be initialized by the cpu via the i2c interface or i2c driver before the video data is captured. the following settings are needed. data output format : any mode of ntsc data size : vga/qvga/any output format : interlaced/non-interlaced interface : 8-bit video stream contrast : any rev. 2.0, 09/02, page 365 of 366 luminance : any hue : any the data size should be specified as the maximum size except where the reduction size for video capture cannot be specified. however, when the size in the y direction is specified in the video decoder, an external circuit in which the vhs and vqclk signals are not output on the inv alid line may be required. contrast, luminance, and hue values for the sequence of images to be captured should be specified to registers in the video decoder. rev. 2.0, 09/02, page 366 of 366 appendix k product lineup operating temperature electrical characteristics reliability hd64413asf regular specification products 0 c to + 70 c shown in section 7 standard hd64413asfi wide-range specification products - 40 c to + 85 c shown in section 7 ta = - 40 c to + 85 c standard hd64413asfd high reliability products for automobile application - 40 c to + 85 c shown in section 7 ta = - 40 c to + 85 c high reliability hd64413a q2sd user's manual publication date: 1st edition, october 1999 2nd edition, september 2002 published by: business operation division semiconductor & integrated circuits hitachi, ltd. edited by: technical documentation group hitachi kodaira semiconductor co., ltd. copyright ? hitachi, ltd., 1999. all rights reserved. printed in japan. |
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